dts: nios2f: Add device tree support
Add device tree support for nios2f soc Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
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parent
6d4d8ce026
commit
8f908f38e0
6 changed files with 56 additions and 10 deletions
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@ -49,12 +49,8 @@ config UART_NS16550_PORT_0
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if UART_NS16550_PORT_0
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config UART_NS16550_PORT_0_NAME
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default "UART_0"
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config UART_NS16550_PORT_0_IRQ_PRI
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default 3
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config UART_NS16550_PORT_0_BAUD_RATE
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default 115200
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config UART_NS16550_PORT_0_OPTIONS
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default 0
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11
arch/nios2/soc/nios2f-zephyr/dts.fixup
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11
arch/nios2/soc/nios2f-zephyr/dts.fixup
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@ -0,0 +1,11 @@
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#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE NS16550_F0008000_CURRENT_SPEED
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#define CONFIG_UART_NS16550_PORT_0_NAME NS16550_F0008000_LABEL
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#define _RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
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#define _RAM_SIZE (CONFIG_SRAM_SIZE * 1024)
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#define _ROM_ADDR CONFIG_FLASH_BASE_ADDRESS
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#define _ROM_SIZE (CONFIG_FLASH_SIZE *1024)
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@ -9,8 +9,3 @@
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#define _RESET_VECTOR ALT_CPU_RESET_ADDR
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#define _EXC_VECTOR ALT_CPU_EXCEPTION_ADDR
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#define _ROM_ADDR ONCHIP_FLASH_0_DATA_BASE
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#define _ROM_SIZE ONCHIP_FLASH_0_DATA_SPAN
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#define _RAM_ADDR ONCHIP_MEMORY2_0_BASE
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#define _RAM_SIZE ONCHIP_MEMORY2_0_SPAN
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@ -9,5 +9,5 @@
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*/
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#include <layout.h>
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#include <generated_dts_board.h>
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#include <arch/nios2/linker.ld>
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43
dts/nios2/nios2f.dtsi
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43
dts/nios2/nios2f.dtsi
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@ -0,0 +1,43 @@
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#include "skeleton.dtsi"
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#define __SIZE_K(x) (x * 1024)
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "altera,nios2f";
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reg = <0>;
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};
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};
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flash0: flash@0 {
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reg = <0x00 0xb8000>;
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};
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sram0: memory@400000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x400000 0x20000>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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uart0: uart@f0008000 {
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compatible = "ns16550";
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reg = <0xf0008000 0x400>;
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label = "UART_0";
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status = "disabled";
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};
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};
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};
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@ -16,6 +16,7 @@
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#include <system.h>
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#include <arch/nios2/asm_inline.h>
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#include <generated_dts_board.h>
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#include "nios2.h"
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#ifdef __cplusplus
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