From 8f908f38e0c3464359c10928340b4a8c6e091089 Mon Sep 17 00:00:00 2001
From: Savinay Dharmappa <savinay.dharmappa@intel.com>
Date: Fri, 20 Apr 2018 21:48:10 +0530
Subject: [PATCH] dts: nios2f: Add device tree support

Add device tree support for nios2f soc

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
---
 .../nios2/soc/nios2f-zephyr/Kconfig.defconfig |  4 --
 arch/nios2/soc/nios2f-zephyr/dts.fixup        | 11 +++++
 arch/nios2/soc/nios2f-zephyr/include/layout.h |  5 ---
 arch/nios2/soc/nios2f-zephyr/linker.ld        |  2 +-
 dts/nios2/nios2f.dtsi                         | 43 +++++++++++++++++++
 include/arch/nios2/arch.h                     |  1 +
 6 files changed, 56 insertions(+), 10 deletions(-)
 create mode 100644 arch/nios2/soc/nios2f-zephyr/dts.fixup
 create mode 100644 dts/nios2/nios2f.dtsi

diff --git a/arch/nios2/soc/nios2f-zephyr/Kconfig.defconfig b/arch/nios2/soc/nios2f-zephyr/Kconfig.defconfig
index e9284b1559c..67f69b4b029 100644
--- a/arch/nios2/soc/nios2f-zephyr/Kconfig.defconfig
+++ b/arch/nios2/soc/nios2f-zephyr/Kconfig.defconfig
@@ -49,12 +49,8 @@ config UART_NS16550_PORT_0
 
 if UART_NS16550_PORT_0
 
-config UART_NS16550_PORT_0_NAME
-	default "UART_0"
 config UART_NS16550_PORT_0_IRQ_PRI
 	default 3
-config UART_NS16550_PORT_0_BAUD_RATE
-	default 115200
 config UART_NS16550_PORT_0_OPTIONS
 	default 0
 
diff --git a/arch/nios2/soc/nios2f-zephyr/dts.fixup b/arch/nios2/soc/nios2f-zephyr/dts.fixup
new file mode 100644
index 00000000000..ff0fd7ec1eb
--- /dev/null
+++ b/arch/nios2/soc/nios2f-zephyr/dts.fixup
@@ -0,0 +1,11 @@
+#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE	NS16550_F0008000_CURRENT_SPEED
+
+#define CONFIG_UART_NS16550_PORT_0_NAME		NS16550_F0008000_LABEL
+
+#define _RAM_ADDR				CONFIG_SRAM_BASE_ADDRESS
+
+#define _RAM_SIZE				(CONFIG_SRAM_SIZE * 1024)
+
+#define _ROM_ADDR				CONFIG_FLASH_BASE_ADDRESS
+
+#define _ROM_SIZE				(CONFIG_FLASH_SIZE *1024)
diff --git a/arch/nios2/soc/nios2f-zephyr/include/layout.h b/arch/nios2/soc/nios2f-zephyr/include/layout.h
index fbb21e15764..6fa00884b5b 100644
--- a/arch/nios2/soc/nios2f-zephyr/include/layout.h
+++ b/arch/nios2/soc/nios2f-zephyr/include/layout.h
@@ -9,8 +9,3 @@
 #define _RESET_VECTOR		ALT_CPU_RESET_ADDR
 #define	_EXC_VECTOR		ALT_CPU_EXCEPTION_ADDR
 
-#define _ROM_ADDR		ONCHIP_FLASH_0_DATA_BASE
-#define _ROM_SIZE		ONCHIP_FLASH_0_DATA_SPAN
-
-#define _RAM_ADDR		ONCHIP_MEMORY2_0_BASE
-#define _RAM_SIZE		ONCHIP_MEMORY2_0_SPAN
diff --git a/arch/nios2/soc/nios2f-zephyr/linker.ld b/arch/nios2/soc/nios2f-zephyr/linker.ld
index 47da5767acc..31b9b0621a9 100644
--- a/arch/nios2/soc/nios2f-zephyr/linker.ld
+++ b/arch/nios2/soc/nios2f-zephyr/linker.ld
@@ -9,5 +9,5 @@
  */
 
 #include <layout.h>
-
+#include <generated_dts_board.h>
 #include <arch/nios2/linker.ld>
diff --git a/dts/nios2/nios2f.dtsi b/dts/nios2/nios2f.dtsi
new file mode 100644
index 00000000000..b21a54b5556
--- /dev/null
+++ b/dts/nios2/nios2f.dtsi
@@ -0,0 +1,43 @@
+#include "skeleton.dtsi"
+
+#define __SIZE_K(x) (x * 1024)
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "altera,nios2f";
+			reg = <0>;
+		};
+
+	};
+
+	flash0: flash@0 {
+		reg = <0x00 0xb8000>;
+	};
+
+	sram0: memory@400000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0x400000 0x20000>;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		uart0: uart@f0008000 {
+			compatible = "ns16550";
+			reg = <0xf0008000 0x400>;
+			label = "UART_0";
+
+			status = "disabled";
+		};
+
+	};
+};
diff --git a/include/arch/nios2/arch.h b/include/arch/nios2/arch.h
index 2d59b61ffa0..6e420264ae3 100644
--- a/include/arch/nios2/arch.h
+++ b/include/arch/nios2/arch.h
@@ -16,6 +16,7 @@
 
 #include <system.h>
 #include <arch/nios2/asm_inline.h>
+#include <generated_dts_board.h>
 #include "nios2.h"
 
 #ifdef __cplusplus