hwmv2: Introduce Hardware model version 2 and convert devices
This is a squash of the ``collab-hwm`` branch which converts all
in-tree boards to hardware model version 2 including build system
changes, board updates and soc conversions.
This squash is a combination of the following commits:
ca214745a1 soc: Remove soc_legacy folder and move ARM Kconfig
f12cb0979f scripts: ci: check_compliance: remove HWMv1 checks
1807bcf4d4 boards: mimx8mq_evk: port to HWMv2
3ec2299c62 soc: nxp: port imx8mq SOC to HWMv2
8ea02f4e63 boards: verdin_imx8mp: convert to HVMv2
f2eb7652ce boards: phyboard_pollux: move to HVMv2
ab509a5ee0 boards: nxp: mimx8mp_evk: port M7 core to HWMv2
06ad037f99 soc: nxp: imx8mp: port M7 core to HWMv2
3f9e706859 boards: mimx8mm_phyboard: convert to HVMv2
204372d264 boards: imx8mm_evk: port CM4 core to HWMv2
f82c961a46 soc: nxp: imx8mm: port iMX8MM M4 core to HVMv2
6987b2e305 boards: pico_pi: convert to HVMv2
84484e6707 boards: warp7: convert to HWMv2
ae443d1e3c boards: meerkat96: port to HWMv2
e3629c64e6 boards: colibri_imx7d: port to HWMv2
fc835d893d soc: nxp: convert iMX7 Dual core to HWMv2
29ef2f23eb boards: udoo_neo_full: convert to HWMv2
fd49b1749e soc: nxp: convert iMX6 SoloX core to HWMv2
1e59b7a3fd soc: nxp: imxrt11xx: only set
CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION for M7
69bb0eb258 hwmv2: MAINTAINERS: Fix NXP maintainer yaml
1c4458890f boards: firefly: roc_rk3568_pc: Fix SMP configuration
651a4370ad boards: Fix variants and revisions
196cfda66d tests/samples: Drop default revision identifiers
6ec6b1d75a boards: Drop revision from twister identifiers for
default revisions
b774cdd59f scripts: utils: board_v1_to_v2: drop board_legacy prefix
7aa36e6640 boards: riscv: esp32c3_luatos_core: make usb variant
fe25709a9c twister: add unit_testing soc and board
f88f211b4e scripts: ci: check_compliance: improve the "not sorted"
command
b21a455dfb bluetooth: controller: Fix openisa checks
fdc76c48a7 workflow: compliance: Add rename limit
14ecafc67d dts: bindings: vendor-prefixes: Sort entries
dbc366c3c7 soc: nxp: lpc: Move wrong configurations
8e02c08f96 maintainers: Fix invalid paths
b1b85e2495 boards: up: Fix spaces
58cc4013b3 maintainers: Fix xen path
66ce5c0b09 boards/soc: Add missing copyright headers
bb47243254 boards: qemu: x86: Remove pointless file
2e816a8a3a samples: tests: update esp32-based board naming
9aeab17139 samples: tests: remove platform_exclude of esp32 boards
a4fe97b9de boards: shields: m5stack_core2_ext: update board name
615fcab94a samples: ipm_esp32: fix board labels and skip testing
7752f69b7f boards: legacy: remove index entry for xtensa/riscv
boards.
3eba827956 MAINTAINERS: update Espressif entries
914362bbd5 boards: xtensa: yd_esp32: Convert to v2
a62278fd23 boards: xtensa: xiao_esp32s3: Convert to v2
b6a11ccec4 boards: xtensa: olimex_esp32_evb: Convert to v2
c1067c16d2 boards: xtensa: odroid_go: Convert to v2
b8340b0109 boards: xtensa: m5stickc_plus: Convert to v2
9d81e417be boards: xtensa: m5stack_stamps3: Convert to v2
c296672720 boards: xtensa: m5stack_core2: Convert to v2
fada12aa9d boards: xtensa: m5stack_atoms3_lite: Convert to v2
fe37ebac1e boards: xtensa: m5stack_atoms3: Convert to v2
d32828fe6a boards: xtensa: kincony_kc868_a32: Convert to v2
5afba7855b boards: xtensa: heltec_wireless_stick_lite_v3: Convert to
v2
ca48c17723 boards: xtensa: heltec_wifi_lora32_v2: Convert to v2
db1fd4d229 boards: xtensa: esp32s3_luatos_core: Convert to v2
a78b2552eb boards: xtensa: esp32s3_devkitm: Convert to v2
cc96061d96 boards: xtensa: esp32s2_saola: Convert to v2
ed854e05d1 boards: xtensa: esp32s2_lolin_mini: Convert to v2
4fa1ae8110 boards: xtensa: esp32s2_franzininho: Convert to v2
5543040a18 boards: xtensa: esp_wrover_kit: Convert to v2
2335ae79b3 boards: xtensa: esp32_ethernet_kit: Convert to v2
f910b7ad4f boards: xtensa: esp32_devkitc_wrover: Convert to v2
32104db555 boards: xtensa: esp32_devkitc_wroom: Convert to v2
e23a41200d boards: riscv: icev_wireless: Convert to v2
3c670e4e53 boards: riscv: xiao_esp32c3: Convert to v2
fc7c6a060b boards: riscv: stamp_c3: Convert to v2
22c2edb89c boards: riscv: esp32c3_luatos_core: Convert to v2
0a96dcb778 boards: riscv: esp32c3_devkitm: Convert to v2
be1ee1c446 vendors: update vendors lists
5e6c62137f soc: espressif_esp32: Port to HWMv2
037a3b52a4 boards: Raspberry Pi pico pwm led adjustment
7277cae6fa samples: blinky_pwm: enable pwm_leds in rpi_pico overlay
da3e49d34e boards: nxp: update selection of
FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET
bc8424dd3b soc: nxp: imxrt: move FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET
to SOC level
041cb52939 soc: brcm: bcm_vk: Rename to bcnvk
576b43a95c soc: Fix SOC_FAMILY name mismatches
e8f3e6494d hwmv2: boards: intel: adsp: Fix runner after paths
renamed
550399e927 boards: weact: stm32g431_core: Add wrongly deleted file
back
08708c909e tests: drivers: flash: Renamed missed board rename
06dac41e68 hwmv2: Convert Seagate Faze board to hwmv2
dd8f842b40 hwmv2: nxp: update MAINTAINER paths for hwmv2
b4d1c04978 hwmv2: lpc: updated overlay and conf files in samples and
tests
067c69089e boards: nxp: convert lpcxpresso55s69 to hwmv2
097205b40a hwmv2: Global fix of lpc54114_m4 overlay and conf files
d8cfa6fb29 boards: nxp: convert lpcxpresso54114 to hwmv2
c29ed228c6 boards: nxp: convert lpcxpresso55s36 to hwmv2
88cfd3d6ac boards: nxp: convert lpcxpresso55s28 to hwmv2
ad30c940ee boards: nxp: convert lpcxpresso55s16 to hwmv2
9e5a10ec80 boards: nxp: convert lpcxpresso55s06 to hwmv2
5650c83268 boards: nxp: convert lpcxpresso51u68 to hwmv2
82cf44be45 boards: nxp: convert lpcxpresso11u68 to hwmv2
1a9c405a6f soc: nxp: convert LPC SOC family to hardware model V2
f2b536d253 boards: intel: doc: hwmv2: Fix some renamed paths
5ee6058710 samples/tests: Use board revisions
b76687602f boards: Add yaml files for boards missing revisions
32ae4918d0 boards: nordic: Fix board names
cc1dabca65 MAINTAINERS: Update for renamed folders
a37ddce659 soc: xilinx: Rename to xlnx
a1393a07f6 soc: xenvm: Rename to xen
813ed00f67 soc: raspberry_pi: Rename to raspberrypi
71317d6798 soc: cadence: Rename to cdns
8cb0c51ec6 soc: broadcom: Rename to brcm
2b9db15c69 soc: andes: Rename to andestech
0101216ce1 soc: altera: Rename to altr
4b4c3ca65d boards: wurth_elektronik: Rename to we
cdc3ef499f boards: ublox: Rename to u-blox
cabdd4ad05 boards: space_cubics: Rename to sc
4b5bd7ae8a boards: seeed_studio: Rename to seeed
a992785ceb boards: raspberry_pi: Rename to raspberrypi
3c1cdc20fe boards: laird_connect: Rename to lairdconnect
291c7cde2b boards: cadence: Rename to cdns
95db897526 boards: broadcom: Rename to brcm
0a47b94879 boards: beagleboard: Change to beagle
9f9f221c24 boards: andes: Rename to andestech
e7869ca38a boards: altera: Rename to altr
bf2fb5eca3 various: Change SOC_FAMILY_NRF to SOC_FAMILY_NORDIC_NRF
e25730ba56 modules: tf-m: Rename from nordic_nrf to nordic
9e3466606a boards: nordic_nrf: Rename to nordic
09a398dcc8 soc: nordic_nrf: Rename to nordic
cb8ffc74f8 boards: renode: Add documentation index
2291ff4b55 boards: arm: riscv32_virtual: Convert to v2
484b7f1996 soc: riscv_renode_virtual: Port to HWMv2
cc5c2fb0c7 soc: raspberry_pi: Fix SOC_SERIES and SOC mismatch
59cb580513 soc: arm: designstart: Fix SOC_SERIES and SOC mismatch
aa9e0de7af samples: Fix invalid links
a1480cf1cf maintainers: Fix paths
0d719e004b boards: Update documentation links
eb5c3e6f79 boards: wurth_elektronik: Drop duplicate prefix
a34a3640b7 boards: waveshare: Drop duplicate prefix
cf50e950e7 boards: weact: Drop duplicate prefix
737cfb548f boards: sparkfun: Drop duplicate prefix
505494c97a boards: segger: Drop duplicate prefix
4eaf69f37a boards: ruuvi: Drop duplicate prefix
a1335caeae boards: ronoth: Drop duplicate prefix
a9f7f30bf6 boards: raytac: Drop duplicate prefix
80db4c81b3 boards: qemu: Drop duplicate prefix
433d7e9976 boards: particle: Drop duplicate prefix
4ea79d19e7 boards: olimex: Drop duplicate prefix
fd4ae6f6a8 boards: mikroe: Drop duplicate prefix
36080549bd boards: khados: Drop duplicate prefix
169bf8ae1d boards: intel: Drop duplicate prefix
25f04d5222 boards: holyiot: Drop duplicate prefix
11c2af0de8 boards: google: Drop duplicate prefix
d5128f4016 boards: ebyte: Drop duplicate prefix
44fbc68cad boards: dragino: Drop duplicate prefix
f7fe431b44 boards: contextual_electronics: Drop duplicate prefix
9094fea63b boards: circuit_dojo: Drop duplicate prefix
b632acc1fc boards: blue_clover: Drop duplicate prefix
1a3316ebdc boards: bbc: Drop duplicate prefix
71c0344f8c boards: arduino: Drop duplicate prefix
f0176fc25f boards: altera: Drop duplicate prefix
36b920ed0f boards: adi: Drop duplicate prefix
22520368d9 boards: adafruit: Drop duplicate prefix
296acfb2bc boards: actinius: Drop duplicate prefix
55063380b7 boards: 96boards: Drop duplicate prefix
1f93394b55 boards: nxp: convert mimxrt595_evk to hardware model v2
e7a4fd2ec1 soc: nxp: rt5xx: convert RT5xx SOC to HWMv2
01942f1d11 twister: normalize platform name when storing files/data
477c8b84dd twister: tests: test with slashes in platform names
64e3e816c4 soc: Add include guards
3a7aa2fa49 gitignore: update the compliance file list
84e1c17ad9 scripts: ci: check_compliance: add a check for board yml
file
a90f53ad57 boards: sync up the vendor tags and vendor-list
af9aa65299 dts: vendor-prefixes: add keep-sorted markers
50f0bf05a3 dts: vendor-prefixes: sort the vendor list
a10b614aa4 dts: vendor-prefixes: ensure all prefixes are lowercase
5abe735e93 manifest: update SOF sha for NXP HWMv2
9ab8f64ca9 modules: rename SOC_FAMILY_IMX
483ff8dd4d modules: mcux: remove SOC_FAMILY_NXP_ADSP
f113dd5342 samples: update board name
39b31287d9 boards: nxp: Convert i.MX ADSP boards to hardware model
v2
1511e356a2 soc: nxp: Port i.MX ADSP family to hardware model v2
c91e25ab47 soc: mec: rename all mec1501x reference to mec15xx
1c231fd939 hwmv2: boards: Convert IMXRT boards
417cff1e60 hwmv2: soc: Port IMXRT family to HWMV2
28d4e41b1b hwmv2: clean up arm64 soc and board empty directory
2b520f83cb hwmv2: port NXP SoC LS1046A to V2
bf7899c645 hwmv2: port nxp_ls1046ardb board to V2
33f7b61866 samples/tests: Rename numaker boards
8f20ea6e93 boards: nuvoton: numaker_pfm: Split into 2 boards
7cf4ff43a1 drivers: pinctrl: imx: align with hwm v2
c68e1fea4e drivers: clock_control: ccm_rev2: align with hwm v2
update
3b49014a0f hwmv2: move imx8mn EVK board to V2
14f344eeab hwmv2: move imx8mp EVK board to V2
40f3f8f22d hwmv2: move imx8mm EVK board to V2
10bf79ea51 hwmv2: move imx8m soc for a-core to V2
8727d5ca80 hwmv2: move imx93 EVK board to V2
c81ef01563 hwmv2: move imx93 soc to V2
5836c1b699 modules: mcux: introduce CONFIG_MCUX_CORE_SUFFIX
338f6f2bf1 doc: update board porting guide to match new hardware
model
9639a1b5dc soc: silabs: drop useless defconfigs
981807444e soc: silabs: introduce SOC_GECKO_SDID
5d07e82485 soc: silabs: SOC_FAMILY_* replace SOC_GECKO_SERIES*
2fd081ac86 soc: silabs: align comments with soc tree
66d425f571 soc: silabs: split in families
5bd38f47a9 arch: arch: kconfig: Fix wrong placement of endmenu
00c6ef25be tests/samples: Rename overlay files for renamed boards
0c639b8378 boards: Fix bools and selections
c2ef907d1d drivers: flash: it8xxx2: Add missing Kconfigs
553de2ebc9 soc: ite: ec: it8xxx2: Fix SOC_SERIES being in wrong file
b8ec0080c2 boards: Documentation link fixes
eb7025e50f tests: Update board names for hwmv2
10ef3d4bd2 boards: silab: Add documentation index file
ba9fdaa1d6 boards: arm: efr32_radio: Convert to v2
86c8d4a0ca boards: arm: efm32pg_stk3402a: Convert to v2
575ac5cafb manifest: Update hal_silabs
87b2907304 boards: arm: efr32_thunderboard: Convert to v2
14b30055ab boards: arm: efr32mg_sltb004a: Convert to v2
0012bfc15d boards: arm: efr32xg24_dk2601b: Convert to v2
f526225ead boards: arm: efm32wg_stk3800: Convert to v2
19e7df29df boards: arm: efm32pg_stk3401a: Convert to v2
0bd7d963d6 boards: arm: efm32hg_slstk3400a: Convert to v2
795a90f9bf boards: arm: efm32gg_stk3701a: Convert to v2
43d5540be7 boards: arm: efm32gg_slwstk6121a: Convert to v2
065148d856 boards: arm: efm32gg_sltb009a: Convert to v2
1dc9a8aa17 soc: silabs_exx32: Port to HWMv2
763571e878 tests: Expand names
dae301b8a3 boards: xen: xenvm: Expand name
19e60eef36 boards: qemu: qemu_cortex_a53: Expand names
a0a7c30f28 soc: intel: intel_adsp: Fix issues
df9a4223fe scripts: ci: introduce soc name check in check_compliance
ed401abaff soc: emsdsp: align SoC name defined in soc.yml to Kconfig
SOC setting
fc78e5eaa4 MAINTAINERS: update RISC-V arch area paths
4e586958ff boards: convert QEMU RISC-V 64 bit board to Zephyr HWMv2
f4c31a2b86 boards: convert QEMU RV32E board to Zephyr HWMv2
5b2ffc652b boards: convert QEMU RISC-V 32 bit board to Zephyr HWMv2
5db061a4c6 soc/riscv: convert the QEMU virt RISCV-32 SoC to HWMv2
6547845e9d boards: convert SparkFun RED-V Things Plus to Zephyr
HWMv2
95a1f96399 boards: convert SiFive HiFive Unmatched to Zephyr HWMv2
e563eb0a62 soc/sifive/sifive_freedom: add SiFive Freedom FU740 SoC
8914bc58b6 boards: convert SiFive HiFive Unleashed to Zephyr HWMv2
7e8de1e781 soc/sifive/sifive_freedom: add SiFive Freedom U540 SoC
bfcc2ed18f boards: convert SiFive HiFive1 Rev. B to Zephyr HWMv2
330fc38f9f boards: convert SiFive HiFive1 to Zephyr HWMv2
b9e06f4c38 soc/sifive/sifive_freedom: add SiFive Freedom E310 SoC
4b90b30b9d scripts: west_commands: completion: Add hwmv2 complete to
fish
0f6842e2fa scripts: west_commands: completion: Add hwmv2 complete to
zsh
b2af1e1737 scripts: west: list_boards: Fix hwmv2 output
686a4b78b8 scripts: west_commands: completion: Add hwmv2 complete to
bash
396b6bb856 soc: nxp: fix typo in SoC name
765299c627 soc: broadcom: align SoC names defined in soc.yml to
Kconfig SOC setting
7efd46eb41 soc: arm: align SoC names defined in soc.yml to Kconfig
SOC setting
505cbc5c42 soc: mec: align SoC names defined in soc.yml to Kconfig
SOC setting
951a140701 soc: ti: define SOC name in Kconfig
a795d28810 snippets: Initial HWMv2 support
f9a957e6f6 boards: nordic: nrf9160dk: Fix missing nrf52840 config
df994e7ee8 soc: xilinx: zync7000: Remove xilinx from soc series name
8dfabd56ca soc: cypress: Add protection guard to file
447b951593 tests: kernel: tickless: Remove old board name
bad5dfa71f boards: nordic: nrf5340dk: Fix board names
ad2e863f39 soc: atmel: Use new family prefix
3f08e714b2 soc: intel_adsp: hwmv2: Align SOC_SERIES_INTEL_ACE name
and value
6734597a76 soc: intel_adsp_cavs: hwmv2: Align SOC_SERIES name and
value
2908af0bcc boards: nrf51dk/dongle: change SoC to nRF51822
d1ceb29fca soc: align CONFIG_SOC values to match soc.yml names
4768ccaf70 tests: drivers: gpio: gpio_api_1pin: exclude hifive1
ebdb0879ad boards: nxp: s32z2xxdc2: convert to hwmv2
ae82580d08 boards: nxp: mr_canhubk3: convert to hwmv2
c5f0defbae boards: nxp: ucans32k1sic: convert to hwmv2
1e46cabce6 soc: nxp: convert NXP S32 family to hwmv2
f2f85133f2 soc: stm32: Rename series path
86642f4e78 soc: stm32: Rename Kconfig SOC_SERIES symbols
c61e807896 soc: stm32: Cleanup Kconfig.defconfig files
ca46c8abc9 tests: Fix board names
fbfed5f48f maintainers: Update synopsys entries
8cd8b1cc47 boards: synopsys: Add documentation index
6f6cc57a04 boards: arc: hsdk4xd: Convert to v2
c4c14a54ca soc: snps_arc_hsdk4xd: Port to HWMv2
06c2054e5c boards: arc: iotdk: Convert to v2
ff0e0fce1b soc: snps_arc_iot: Port to HWMv2
334264c46a boards: arc: emsdp: Convert to v2
8b947a0e91 soc: snps_emsdp: Port to HWMv2
990417bbde tests: Update board names for hwmv2
e12719154a boards: arc: em_starterkit: Convert to v2
437a430fbe soc: snps_emsk: Port to HWMv2
f93387f968 boards: arc: hsdk: Convert to v2
1cf2498b13 soc: snps_arc_hsdk: Port to HWMv2
47abe81256 boards: arc: nsim: Convert to v2
1e33786dc4 soc: snps_nsim: Port to HWMv2
7f081914db boards: arc: qemu_arc: Convert to v2
bc97349dbd soc: snps_qemu: Port to HWMv2
a9902ff58e boards: Use zephyr_file for file links
126e1a4e72 boards: Fix invalid documentation links
899f0257c3 boards: stm32wb: Restore missing .defconfig files
790c10b1ee soc: x86/atom: imply mmu, do not select it
faee62088d boards: x86: remove qemu_x86_tiny_768
c34d186a57 x86: atom: remove soc.h with unused content
1be3a9e9d3 x86: remove legacy ia32, use atom instead
60e6b400f9 boards: qemu: move qemu_x86 -> x86
c4fbac27e8 boards: infineon: Add documentation index
b4dd29a9c4 maintainers: Update paths for hwmv2
380f5fdb2b boards: cypress: Add documentation index
9de981be05 boards: arm: xmc47_relax_kit: Convert to v2
6394e8a348 boards: arm: xmc45_relax_kit: Convert to v2
04dbf17e19 soc: xmc_4xxx: Port to HWMv2
c9731f1bce boards: arm: cy8cproto_063_ble: Convert to v2
53d41869d1 boards: arm: cy8cproto_062_4343w: Convert to v2
46c4f01427 boards: arm: cy8ckit_062s4: Convert to v2
d285e19cf2 boards: arm: cy8ckit_062_wifi_bt: Convert to v2
2bebd7298c boards: arm: cy8ckit_062_ble: Convert to v2
af243274c2 soc: psoc6 and psoc_6: Port to HWMv2
105a2bae84 cmake: modules: boards: Fix board deprecation for HWMv2
dca54e000a cmake: modules: boards: Enhance board aliases for HWMv2
fc314e8e3f cmake: modules: boards: Fix BOARD_ALIAS
9a7c2ce6d5 soc: gaisler: Move Kconfig file
1ac56d0501 soc: soc_legacy: mips: Remove out file
c054381a7a boards: adjust few boards/ paths
4d93b8d9fd boards: convert all microchip MEC boards to hwmv2
ab2fcb1245 soc: convert microchip_mec to hwmv2
ead4b57a7b soc: arm64: intel_socfpga: hwmv2: Rename SoCs
d4c143d306 MAINTAINERS: intel_socfpga: Adjust to HWMv2 move
70a66ac03a boards: arm64: intel_socfpga: Move boards to
subdirectories
8a85c07799 boards: arm64: intel_socfpga_agilex5_socdk: move to HWMv2
8c253a99fc boards: arm64: intel_socfpga_agilex_socdk: move to HWMv2
ab883b8019 soc: arm64: intel_socfpga: Move and convert to HWMv2
7c8b7a153b soc: arm: intel_socfpga_std: Rename with HWMv2
8dc2b911f6 soc: board: intel_socfpga_std: Align names to 'Cyclone V'
402366117a soc: arm: intel_socfpga_std: Align board subdirectory
f0a8d12745 boards: arm: cyclonev_socdk: Move to HWMv2
2271f17a86 soc: arm: intel_socfpga_std: Move and convert to HWMv2
841c2a9d99 boards: riscv: beaglev_fire: Convert to v2
3b314531ab boards: riscv: mpfs_icicle: Convert to v2
d4ea2bf70b boards: riscv: m2gl025_miv: Convert to v2
5256e9fcc3 soc: microchip_miv: Port to HWMv2
18e5cf1d51 maintainers: Update path for hwmv2
eab8628f98 boards: arm: qemu_cortex_m3: Convert to v2
1532f2fee1 soc: ti_lm3s6965: Port to HWMv2
430ca6a475 maintainers: Update ambiq paths
a9b9b41b91 boards: ambiq: Add index
db0271ecbb boards: arm: apollo4p_blue_kxr_evb: Convert to v2
957e2b2061 boards: arm: apollo4p_evb: Convert to v2
5a90a44454 soc: ambiq: Port to HWMv2
a20c113fbd boards: nxp: convert ip_k66f to hwmv2
34e3852a54 boards: nxp: convert usb_kw24d512 to hwmv2
20ad604de6 boards: nxp: convert twr_kv58f220m to hwmv2
2e2a7b7656 boards: nxp: twr_ke18f: convert to hwmv2
f7dcc2eb5e boards: nxp: convert rddrone_fmuk66 to hwmv2
b58e90a2e9 boards: nxp: convert hexiwear to hwmv2
aae6e9e454 boards: nxp: frdm_kw41z: convert to hwmv2
1d3baac2d6 boards: nxp: convert frdm_kl25z to hwmv2
3b1d21483f boards: nxp: frdm_k82f: port to hwmv2
6046e6ded9 boards: nxp: port frdm_k64f to hwmv2
0a7bf9fd79 boards: nxp: port frdm_k22f to hwmv2
dce697c823 boards: nxp: add toctree placeholder
666a353409 soc: nxp: kinetis: convert kinetis SOC family to hardware
model V2
89f0a6034b maintainers: Update paths for renesas boards/socs
004bd43c48 tests/samples/snippets: Update board names for hwmv2
a6d756923d boards: arm and arm64: rcar_h3ulcb: Convert to v2
3801216b8d boards: arm64: rcar_salvator_xs_m3: Convert to v2
b7cc30aaea boards: arm: rcar_h3_salvatorx_cr7: Convert to v2
866427ea29 boards: arm: arduino_uno_r4: Convert to v2
2689b3f0ee soc: ra: Port to HWMv2
e7ebc727c8 boards: arm: da1469x_dk_pro: Convert to v2
903265b2bb boards: arm: da14695_dk_usb: Convert to v2
529a78ed51 soc: smartbond: Port to HWMv2
97cf636ae0 boards: arm: rcar_spider_cr52: Convert to v2
6d0c53f3a1 soc: rcar: Port to HWMv2
44e0aa0668 soc: renesas: rzt2m: Move folder structure for more SoCs
85238fc205 boards: misc: Fixed STM32 based boards doc links
dffc08af56 boards: riscv: niosv_m: move and convert to HWMv2
545093abe4 boards: riscv: niosv_g: move and convert to HWMv2
ecfa192f1b soc: riscv: intel_niosv: move and convert to HWMv2
fd1e8cdc30 hwmv2: sof: intel_adsp: submanifest provisional link
8bf067e625 doc: boards: intel_adsp: Re-order pages
4833275ccd MAINTAINERS: intel_adsp: Adjust to HWMv2 move
b9a70e5ea2 soc: intel_adsp: tools: pylint compliance workaround
18c70cc4bf hwmv2: tests: boards: intel_adsp: Adjust board names
ca52baf9de hwmv2: boards: intel_adsp: Overhaul board configurations
d1b3bcce64 soc: boards: xtensa: intel_adsp_ace: Rename with HWMv2
f362a8ae2c doc: soc: boards: intel_adsp_cavs25: Rename with HWMv2
51dee5da92 tests: samples: boards: intel_adsp_cavs25: Rename with
HWMv2
e66c35e0d0 boards: xtensa: intel_adsp_cavs25: Rename board with
HWMv2
d1491a4810 soc: boards: xtensa: intel_adsp_cavs25: Rename with HWMv2
fa0fca79c4 scripts: west: runners: intel_adsp: Adjust path to HWMv2
acd18bfaf7 boards: xtensa: intel_adsp_ace20_lnl: move and convert to
HWMv2
546c94b958 boards: xtensa: intel_adsp_ace15_mtpm: move and convert
to HWMv2
8aab718c3e boards: xtensa: intel_adsp_cavs25_tgph: change to board
variant
30f17424a4 boards: xtensa: intel_adsp_cavs25: move and convert to
HWMv2
35a97cb524 soc: xtensa: intel_adsp: HWMv2 workaround for SOF config
fdc20fdff6 soc: xtensa: intel_adsp: move and convert to HWMv2
22dc2b6391 cmake: improved board handling for revisions
2f1e33a2e6 cmake: improve arch error message for invalid arch
selection
c47c37d3db sample: basic: blinky_pwm: Exclude rpi_pico w variant
7a788b9a18 boards: raspberry_pi: rpi_pico: Use full name for w
variant
7046b92d41 tests: atmel_sam: adc: Fix sam4e_xpro adc build
253ee9638c tests: atmel_sam0: Update platform name
ccb4c63324 samples: atmel_sam0: Update platform name
2d4acf9230 boards: arduino_nano_33_iot: Convert to HWMv2
a60d28969a boards: arduino_mkrzero: Convert to HWMv2
0409e51d3f boards: arduino_zero: Convert to HWMv2
1b2528df1b boards: wio_terminal: Convert to HWMv2
af1096e7ca boards: ev11l78a: Convert to HWMv2
0b1db9c53d boards: adafruit_trinket_m0: Convert to HWMv2
e9874671e2 boards: adafruit_itsybitsy_m4_express: Convert to HWMv2
ba6c014071 boards: adafruit_grand_central_m4_express: Convert to
HWMv2
33ad4a51ca boards: adafruit_feather_m0_lora: Convert to HWMv2
9812f3d54e boards: adafruit_feather_m0_basic_proto: Convert to HWMv2
c76b1fbeca boards: serpente: Convert to HWMv2
649789e433 boards: seeeduino_xiao: Convert to HWMv2
6b3bdb7364 boards: same54_xpro: Convert to HWMv2
93dda5ee4b boards: samr34_xpro: Convert to HWMv2
e48e1f5d5b boards: samc21n_xpro: Convert to HWMv2
f11cf73df1 boards: saml21_xpro: Convert to HWMv2
ac73ed6dcd boards: samd20_xpro: Convert to HWMv2
0fdbe3552e boards: samd21_xpro: Convert to HWMv2
854cff3905 boards: samr21_xpro: Convert to HWMv2
a87ea5bc0a soc: atmel: sam0: Port to HWMv2
706e5d27cd boards: riscv: neorv32: Convert to v2
d1edcdd088 soc: neorv32: Port to HWMv2
0f7add89ca boards: native_sim/posix: Add 64bit versions as variants
b6edad8d68 soc: soc_legacy: remove the arm/st_stm32 folder
c58e0822a6 boards: Convert nucleo_f207zg to HWM v2
b987093a80 soc: v2: stm32: Migrate STM32F2 series
2096fd4652 samples: bluetooth: hci_uart: Fix wrongly converted board
names
830f9c5a82 MAINTAINERS: Update Atmel entries
527cd9d8cd CODEOWNERS: Update Atmel entries
83af7d0c1c samples: atmel_sam: Update platform name
fd9b84d457 tests: atmel_sam: Update platform name
3c72fe863c boards: arduino_due: Convert to HWMv2
37dfacbf9e boards: RoboKit1: Convert to HWMv2
1108d7b0ed boards: sam_v71_xult: Convert to HWMv2
bed44a5c28 boards: sam_e70_xplained: Convert to HWMv2
40448c5a9f boards: sam4s_xplained: Convert to HWMv2
31273692c0 boards: sam4l_ek: Convert to HWMv2
35b5d33ef0 boards: sam4e_xpro: Convert to HWMv2
3b84b9910a soc: atmel: Port SAM family to HWMv2
da00d0e7b9 boards: Convert nucleo_wba55cg to HWM v2
fb2103f89e boards: Convert nucleo_wba52cg to HWM v2
1f9a533fbc soc: st: stm32: Migrate STM32WBA series
3f92f65b28 boards: fix documentation for alientek and blues boards
7646b74aaf boards: stm32l4: doc: add zephyr_file to defconfig path
fea54ddcd9 boards: Convert adi_eval_adin2111ebz to HWM v2
d47f1878b1 boards: Convert adi_eval_adin1110ebz to HWM v2
ae42be236b boards: Convert swan_r5 to HWM v2
83bd1a9ecc boards: Convert stm32l4r9i_disco to HWM v2
39c26f09ed boards: Convert stm32l496g_disco to HWM v2
29d03c970b boards: Convert stm32l476g_disco to HWM v2
74acec315c boards: Convert sensortile_box to HWM v2
fee6d8676e boards: Convert pandora_stm32l475 to HWM v2
008b5d9392 boards: Convert nucleo_l4r5zi to HWM v2
24e357d623 boards: Convert nucleo_l4a6zg to HWM v2
2c5f9dcce0 boards: Convert nucleo_l496zg to HWM v2
4da061646f boards: Convert nucleo_l476rg to HWM v2
15956a69b8 tests: drivers: flash: stm32: update platform name
80324f7707 boards: Convert nucleo_l452re_p to HWM v2
9893e0d111 boards: Convert nucleo_l452re to HWM v2
46f92b227b boards: Convert nucleo_l433rc_p to HWM v2
ed5d1bb4cd boards: Convert nucleo_l432kc to HWM v2
325f95ec20 boards: Convert nucleo_l412rb_p to HWM v2
d055676307 boards: Convert disco_l475_iot1 to HWM v2
c7a415d92c boards: Convert b_l4s5i_iot01a to HWM v2
d15144f582 soc: st: stm32: Migrate STM32L4 series
a63ff71bcb boards: nrf_bsim: Add new nrf5340 board definitions
b53c6f412c boards: nrf_bsim: Remove redundant option setting
83eb4fc069 MAINTAINERS: intel_ish: Adjust to HWMv2 move
715685b19f boards: x86: intel_ish: move and convert intel_ish boards
to HWMv2
5b9ef94106 soc: x86: intel_ish: move and convert to HWMv2
12b297707a boards: Convert stm32wb5mmg to HWM v2
cdcea932bc boards: Convert stm32wb5mm_dk to HWM v2
0a3ae2b223 boards: Convert nucleo_wb55rg to HWM v2
20b4ce17d5 soc: st: stm32: Migrate STM32WB series
47c65400d6 soc: st: stm32: fix stm32l0 family
59ec56f9e6 boards: Convert stm32h573i_dk to HWM v2
dc5977dbba boards: Convert nucleo_h563zi to HWM v2
a6e4928543 soc: st: stm32: Migrate STM32H5 series
99f248e048 soc: stm32u5: Fix references after conversion to hw
modelv2
15f16834e6 boards: Convert stm32u5a9j_dk to HWM v2
c1ee449ef1 boards: Convert sensortile_box_pro to HWM v2
db4deddf9d boards: Convert nucleo_u5a5zj_q to HWM v2
2fd3ed43d2 boards: Convert nucleo_u575zi_q to HWM v2
902fceb173 boards: Convert b_u585i_iot02a to HWM v2
d716ca1a10 soc: st: Migrate stm32u5 series to new hw model
b7abc89428 hwmv2: boards: x86: doc: Adjust common docs to new
locations
69b334f54b MAINTAINERS: Change paths to native and nrf*bsim boards
614611a528 boards: nrf*_bsim: Convert to HW model v2
5821b9ec2e board: native_sim/posix: Convert to hwmv2
04cbad174e soc: native: Convert to HWMv2
24ca0febfc boards: nrf_bsim: Fix path to pinctrl_soc.h
9a32559a2d cmake: FindHostTools: Fix for hwmv2 for host based
targets
c4b11e0251 boards: longan_nano: port to HWMv2
97edd05be3 boards: gd32vf103c_starter: port to HWMv2
9cf624c410 boards: gd32vf103v_eval: port to HWMv2
b40bf25e5e soc: gd_gd32: reorganize folders
71600d7e95 soc: gd_gd32: move pinctrl_soc.h content back to soc
folder
2bd84a1bc5 soc: gd_gd32: port gd32vf103 series to HWMv2
9dc342143b boards: doc: fix a bunch of broken reference
10392d693d doc: boards: split out shields
b2def8ed3a boards: acrn: fix title
bf7d3efe78 boards: riscv: tlsr9518adk80d: Convert to v2
c579770e1d soc: telink_tlsr: Port to HWMv2
9131540109 soc: stm32h7: Couple of tests fixes following migration
2efcefc089 boards: Convert stm32h7b3i_dk to HWM v2
d9b295a85b boards: Convert stm32h750b_dk to HWM v2
a2f56bdcd5 boards: Convert stm32h747i_disco to HWM v2
00314155df boards: Convert stm32h735g_disco to HWM v2
b08819dff7 boards: Convert nucleo_h7a3zi_q to HWM v2
56456c16e5 boards: Convert nucleo_h753zi to HWM v2
91f9198dc4 boards: Convert nucleo_h745zi_q to HWM v2
96f1bafbf9 boards: Convert nucleo_h743zi to HWM v2
b290f25baa boards: Convert nucleo_h723zg to HWM v2
9fbe6bf191 boards: Convert fk7b0m1_vbt6 to HWM v2
44bcfe57c7 boards: Convert arduino_portenta_h7 to HWM v2
4c86af7eae boards: Convert arduino_opta_m4 to HWM v2
b4f852f738 boards: Convert arduino_giga_r1 to HWM v2
bac9789264 soc: st: Migrate stm32h7 series to new hw model
a954e1722d boards: stm32l0: Cleanup board _defconfig files after
migration
7e8515b241 boards: Convert ronoth_lodev to HWM v2
25246c21ef boards: Convert nucleo_l073rz to HWM v2
09396eb2e6 boards: Convert nucleo_l053r8 to HWM v2
70c004fd83 boards: Convert nucleo_l031k6 to HWM v2
e3daa98e79 boards: Convert nucleo_l011k4 to HWM v2
a2de60c6da boards: Convert dragino_nbsn95 to HWM v2
e877ce9cec boards: Convert dragino_lsn50 to HWM v2
2b50218c23 boards: Convert b_l072z_lrwan1 to HWM v2
4a65f55916 soc: st: Migrate stm32l0 series to new hw model
cc6e6be01f boards: fix few leftover ITE board references
a837303268 soc: stm32: Protect Kconfig symbols by SOC_FAMILY_STM32
88e5959f17 hwm2: Fix unit_testing: it is also a legacy board by now
95e06e8663 cmake: Fix uses of old SOC path
d517d3cc24 soc: set linker script for ra4m1
68f9aeddab soc: ite: add SOC_SERIES_ITE_IT8XXX2 guards around ITE
options
ccf4f48f01 boards: convert ite boards to hwmv2
4a6e286a3b soc: convert ite_ec to hwmv2
12e375f826 doc: handle arch / soc / board docs in new hardware model
b4db917de9 boards: Add documentation index files
d6e0d27efe samples: bluetooth: hci_uart: Fix wrong named files
bc16a7a727 tests: Update board names for hwmv2
2834883843 boards: riscv: rv32m1_vega: Convert to v2
9c68231ba9 soc: openisa_rv32m1: Port to HWMv2
986e9619fd soc: starfive_jh71xx: Port to HWMv2
e82932e787 boards: riscv: litex_vexriscv: Convert to v2
cb9339f88f soc: litex_vexriscv: Port to HWMv2
1cd4c34654 boards: riscv: opentitan_earlgrey: Convert to v2
92eadf06b8 soc: opentitan: Port to HWMv2
a8659e170b boards: riscv: titanium_ti60_f225: Convert to v2
359133d725 soc: efinix_sapphire: Port to HWMv2
6d466429ed soc: soc_legacy: riscv: litex_vexriscv: Add updated paths
a1ff441eb3 boards: riscv: adp_xc7k_ae350: Convert to v2
ef82a8255c soc: ae350: Port to HWMv2
282204758a samples: boards: stm32: ccm: fix include path
8ca9341195 samples: basic: threads: fix broken reference
8a947f446d boards: nrf52840dk: fix rst syntax
324cb41153 boards: nordic_nrf: fix broken references
963c74df1c boards: intel_(ish|adl|ehl|rpl), up_squared: fix include
paths
8d518ce504 boards: legacy: drop empty folders
0fef0cef5b boards: mps2: fix table formatting
e52ccc244f boards: add HWMv2 board index
c7426eca5e boards: arm: add legacy tag
1eba9d8a8f boards: acrn: create vendor folder
8d92edc727 tests: kernel: Adjust qemu_x86_tiny_768 configuration
HWMv2
75117d1b2d scripts: ensure posix path is used with --cmakeformat
0b0384b56a maintainers: update paths after HWMv2 changes
c1b77b223d boards: arm: pan1783: Convert to v2
91a077b2ab boards: posix: nrf_bsim: Update paths
413b6c2a40 cmake: modules: configuration_files: Add board identifier
overlay file
4f572ba24f treewide: Update board names for hwmv2
cb348c7edf boards: arm: nrf54l15pdk_nrf54l15: Convert to v2
811ad90566 boards: arm: nrf54h20pdk_nrf54h20: Convert to v2
d44ef90cf8 soc: nordic_nrf: Migrate nRF54H/nRF54L to v2 and fix nrf
c860f205de boards: arm: nrf9151dk_nrf9151: Convert to v2
fba98a1763 soc: nordic_nrf: Migrate nRF9151 to v2
5c156a2d35 boards: arm: 96b_carbon_nrf51: Convert to v2
cfc47a3a4b boards: arm: nrf9161dk_nrf9161: Convert to v2
37129b4e44 boards: arm: nrf9131ek_nrf9131: Convert to v2
a923beba5d boards: arm: bl5340_dvk: Convert to v2
d242b2703b boards: arm: raytac_mdbt53v_db_40_nrf5340: Convert to v2
9c80d4e644 boards: arm: raytac_mdbt53_db_40: Convert to v2
28268c4938 boards: arm: nrf5340_audio_dk_nrf5340: Convert to v2
33ad2b5bc6 boards: arm: thingy53_nrf5340: Convert to v2
40daa94f2d boards: arm: nrf9160_innblue22: Convert to v2
2b0dbb9d51 boards: arm: nrf9160_innblue21: Convert to v2
ee6f7697ac boards: arm: sparkfun_thing_plus_nrf9160: Convert to v2
594e4bad6b boards: arm: circuitdojo_feather_nrf9160: Convert to v2
a5803ba099 boards: arm: actinius_icarus: Convert to v2
db8c275456 boards: arm: actinius_icarus_bee: Convert to v2
30177cf53d boards: arm: actinius_icarus_som: Convert to v2
486504cf24 boards: arm: actinius_icarus_som_dk: Convert to v2
dd0672a64c boards: arm: nrf9160dk_*: Convert to v2
c1565b3d14 boards: arm: xiao_ble: Convert to v2
6dd2723314 boards: arm: qemu_cortex_m0: Convert to v2
ee1ce24a42 boards: arm: bbc_microbit: Convert to v2
1952d559f2 boards: arm: rm1xx_dvk: Convert to v2
9e12c3d8bd boards: arm: nrf51dongle_nrf51422: Convert to v2
0ffbc1da33 boards: arm: nrf51_blenano: Convert to v2
be52dfb7b6 boards: arm: nrf51_vbluno51: Convert to v2
4c29d1827f boards: arm: nrf51_ble400: Convert to v2
5b4a9556fd boards: arm: raytac_mdbt53_db_40_nrf5340: Fix typo
69e5d87a15 boards: arm: contextualelectronics_abc: Convert to v2
5e4ace1bbe boards: arm: degu_evk: Convert to v2
2762460a64 boards: arm: pan1781_evb: Convert to v2
fdc3913e76 boards: arm: ubx_evkninab1_nrf52832: Convert to v2
9c9c3a09a1 boards: arm: holyiot_yj16019: Convert to v2
109edc296f boards: arm: blueclover_plt_demo_v2_nrf52832: Convert to
v2
7bfcdbbe8f boards: arm: decawave_dwm1001_dev: Convert to v2
0fbb543983 boards: arm: acn52832: Convert to v2
073e0f8080 boards: arm: we_proteus2ev_nrf52832: Convert to v2
197a19f396 boards: arm: ebyte_e73_tbb_nrf52832: Convert to v2
1616fc8ae5 boards: arm: nrf52_vbluno52: Convert to v2
5622077738 boards: arm: nrf52_sparkfun: Convert to v2
a6289516e4 boards: arm: 96b_nitrogen: Convert to v2
439d836883 boards: arm: nrf52_blenano2: Convert to v2
16e65f09c4 boards: arm: arduino_nicla_sense_me: Convert to v2
862efd5a21 boards: arm: thingy52_nrf52832: Convert to v2
dede0f6cd3 boards: arm: nrf52_adafruit_feather: Convert to v2
91e864ea29 boards: arm: nrf52832_mdk: Convert to v2
47ec3e416b boards: arm: ruuvi_ruuvitag: Convert to v2
52f797a227 boards: arm: pinetime_devkit0: Convert to v2
433db339f9 boards: arm: ubx_evkannab1_nrf52832: Convert to v2
a646d3f2d5 boards: arm: ubx_bmd300eval_nrf52832: Convert to v2
d0d434bf86 cmake: print identifier instead of variant
c3f5ed8157 boards: arm: we_proteus3ev_nrf52840: Convert to v2
eecff8ee7a boards: arm: nrf52840_mdk_usb_dongle: Convert to v2
34507614f6 boards: arm: nrf52840_mdk: Convert to v2
f02b56cb96 boards: arm: nrf52840_blip: Convert to v2
600c55c92a boards: arm: nrf52840_papyr: Convert to v2
f294bfc5e4 boards: arm: reel_board: Convert to v2
882524d2a0 boards: arm: nrf21540dk_nrf52840: Convert to v2
4bce0e9b39 boards: arm: nrf52840dongle_nrf52840: Convert to v2
d0229c771f boards: arm: particle_argon: Convert to v2
23a0570e64 boards: arm: particle_boron: Convert to v2
b6d3e1764f boards: arm: particle_xenon: Convert to v2
499f3e7902 boards: arm: rak5010_nrf52840: Convert to v2
9ae6b1804d boards: arm: rak4631_nrf52840: Convert to v2
fe2c90da5c boards: arm: pinnacle_100_dvk: Convert to v2
3d4d46698c boards: arm: ubx_evkninab3_nrf52840: Convert to v2
b1afbf0158 boards: arm: ubx_bmd380eval_nrf52840: Convert to v2
9f9897c872 boards: arm: ubx_bmd345eval_nrf52840: Convert to v2
f7fb2030c7 boards: arm: ubx_bmd340eval_nrf52840: Convert to v2
7186432662 boards: arm: raytac_mdbt50q_db_40_nrf52840: Convert to v2
32c4bdc0c4 boards: arm: pan1780_evb: Convert to v2
7b64c638a8 boards: arm: pan1770_evb: Convert to v2
156ee8ad8a boards: arm: mg100: Convert to v2
3d33dadeb0 boards: arm: arduino_nano_33_ble: Convert to v2
4fee7371d2 boards: arm: adafruit_itsybitsy_nrf52840: Convert to v2
ad37a0c222 boards: arm: adafruit_feather_nrf52840: Convert to v2
cf85b7169f boards: arm: bt510: Convert to v2
44b67ac430 boards: arm: bt610: Convert to v2
7dbb65d371 boards: arm: ubx_evkninab4_nrf52833: Convert to v2
5e79cb957d boards: arm: raytac_mdbt50q_db_33_nrf52833: Convert to v2
12bd83a218 boards: arm: pan1782_evb: Convert to v2
1a135ec352 boards: arm: bbc_microbit_v2: Convert to v2
4dbe97e5ea boards: arm: nrf52833dk: Convert to v2
d632b90043 boards: arm: ubx_bmd360eval_nrf52811: Convert to v2
cc1a30f24b boards: arm: we_ophelia1ev_nrf52805: Convert to v2
df0df9000b boards: arm: ubx_bmd330eval_nrf52810: Convert to v2
d2c7972a9a boards: arm: nrf52dk: Convert to v2
202c2bf447 boards: arm: bl654_sensor_board: Convert to v2
c3e36f2042 boards: arm: bl654_usb: Convert to v2
b9dd58aea1 boards: arm: bl654_dvk: Convert to v2
0e1898b093 boards: arm: bl653_dvk: Convert to v2
286f4a7524 boards: arm: bl652_dvk: Convert to v2
d1709cdb37 boards: update nRF51dk board to board scheme v2.
8f040cff2c boards: Update nrf5340dk_nrf5340 to HWMv2 scheme
8c90fae8e0 boards: update nRF52840dk_nrf52840/nrf52811 board to
board scheme v2.
c828dcc60e boards: common: openocd-nrf5: Add HWMv2 support
c79f1b0d94 kconfig: soc: adopt Nordic SoC series to support hw model
v2 scheme
3584b30fc1 tests: Update board names for hwmv2
94024d940e boards: arm: arty_a7: Convert to v2
8053c3a8df boards: arm: scobc_module1: Convert to v2
d5473b76fe soc: designstart: Port to HWMv2
f5792b05e7 boards: arm: fvp_baser_aemv8r_aarch32: Convert to v2
ff202daa8e soc: fvp_aemv8r_aarch32: Port to HWMv2
e66cbc2945 boards: arm: v2m_musca_s1: Convert to v2
33b47b2edb boards: arm: v2m_musca_b1: Convert to v2
baeebd31d2 soc: musca: Port to HWMv2
73b257a3f9 boards: arm: v2m_beetle: Convert to v2
85de0888ec soc: beetle: Port to HWMv2
867960a891 manifest: Update modules
6ca677ed3a boards: arm: mps2: Convert to v2
bcf4ad19d4 twister: build_dir: convert / to _ to support hwmv2
0ac386683f soc: Kconfig.v2: Add SOC_PART_NUMBER
9242c3c78f soc: stm32: soc.yml: reorder series
248d17f160 boards: stm32: cleanup
0a67265e99 boards: stm32: fix for boards with revisions
f8d44317ee soc: stm32l5: Rename overlays for nucleo_l552ze_q ns
target.
400343d17e soc: stm32: Set default on USE_DT_CODE_PARTITION
d783ef549a soc: stm32l5: Update stm32l5 non secure targets in
various places
643aeac552 boards: Convert stm32l562e_dk to HWM v2
e601d64344 boards: Convert nucleo_l552ze_q to HWM v2
2f7a387b32 soc: st: Migrate stm32l5 series to new hw model
519752efcd boards: xenvm: doc: Remove reference to deleted file
06263dd717 boards: xenvm: Unset HEAP_MEM_POOL_SIZE in gicv3 variant
66b0df5526 boards: qemu_cortex_a53: Fix Kconfig warnings in SMP
variant
fa07bd9419 boards: mps3: Fix non-secure variant
8f6f0726dd boards: Move xenvm under xen
7b155a7031 boards: Raspberry Pi vendor fix
804697afa5 boards: Move 96b_aerocore to 96boards
d2f001e320 boards: x86: acrn: move and convert to HWMv2
ec7f7b3c30 tests: kernel: qemu_x86: adjust to the HWMv2
89dfcddc7e boards: x86: qemu_x86_tiny@768: change to board variant
eb724eb6a7 boards: x86: qemu_x86: optimize default HWMv2
configurations
6f1043cde6 boards: x86: qemu_x86: move and convert to HWMv2
cab924cbfb soc: x86: ia32: move and convert to HWMv2
237fdff918 soc: x86: lakemont: move and convert to HWMv2
03042b7704 boards: move 96b_carbon to 96boards folder
767b94414e boards: rename vendor seeed to seeed_studio
07fa3a3d79 boards: Convert olimex_lora_stm32wl_devkit to HWM v2
ba01d3beca boards: Convert nucleo_wl55jc to HWM v2
7ce84f4041 boards: Convert lora_e5_mini to HWM v2
b988bae576 boards: Convert lora_e5_dev_board to HWM v2
6fbf39c726 soc: v2: stm32: Migrate STM32WL series
4a41878442 soc: st: stm32g4: add missing include
1e79ba15f6 boards: Convert weact_stm32g431_core to HWM v2
ffdcb60185 boards: Convert nucleo_g474re to HWM v2
d6acb08d3e boards: Convert nucleo_g431rb to HWM v2
90e592ffd1 boards: Convert b_g474e_dpow1 to HWM v2
eb8a7e3441 soc: st: stm32: Migrate STM32G4 series
ada469f237 tests: Update board names for hwmv2
0342433187 boards: arm: npcx9m6f_evb: Convert to v2
c10248d964 boards: arm: npcx7m6fb_evb: Convert to v2
21ddc5e6a6 boards: arm: npcx4m8f_evb: Convert to v2
5500f3ef21 soc: npcx*: Port to HWMv2
e7baf09ede soc: m48x: Port to HWMv2
5bae4a6480 boards: arm: numaker_pfm_m467: Convert to v2
3b0bd70c8c soc: m46x: Port to HWMv2
d52eab9e83 boards: Convert stm32g081b_eval to HWM v2
6f2835cb11 boards: Convert stm32g071b_disco to HWM v2
ca36d331d2 boards: Convert stm32g0316_disco to HWM v2
662cc4e09b boards: Convert nucleo_g0b1re to HWM v2
dd9bc29769 boards: Convert nucleo_g071rb to HWM v2
353da23ffb boards: Convert nucleo_g070rb to HWM v2
acc932b424 boards: Convert nucleo_g031k8 to HWM v2
cea9b140fd boards: Convert google_twinkie_v2 to HWM v2
52e025943a soc: st: stm32: Migrate STM32G0 series
1c7347686a ci: update check_compliance to not create duplicate lines
in Kconfig
9debd98799 hwmv2: boards: up_squared_pro_700: Add missed intel_adl
changes
adab07c42f boards: Convert msp_exp432p401r_launchxl to HWM v2
642aacdcdf soc: ti_simplelink: Add missing SoC
48637066d3 boards: Fix file paths in documentation
e983bc2a23 samples/tests: Fix mps3 board name
61e0f32716 boards: Convert stm32f3_seco_d23 to HWM v2
a1688ff641 boards: Convert stm32f3_disco to HWM v2
35fb228599 boards: Convert stm32373c_eval to HWM v2
10e5d1122b boards: Convert nucleo_f334r8 to HWM v2
c319cb19f0 boards: Convert nucleo_f303re to HWM v2
11725ccac1 boards: Convert nucleo_f303k8 to HWM v2
400f7f6a4f boards: Convert nucleo_f302r8 to HWM v2
8d84861390 soc: v2: stm32: Migrate STM32F3 series
85b9eee7e8 boards: arm: kv260_r5: Convert to v2
dafbd638e4 boards: arm: mercury_xu: Convert to v2
3ecd12f415 boards: arm: qemu_cortex_r5: Convert to v2
5db2390e9d soc: xilinx_zyncmp: Port to HWMv2
9ba8195cdc boards: arm: qemu_cortex_a9: Convert to v2
8e94b85361 boards: arm: zybo: Convert to v2
c970127fc2 soc: xilinx_zynq7000: Port to HWMv2
394c75373c boards: arm: ast1030_evb: Convert to v2
f2a1cc8714 soc: ast10x0: Port to HWMv2
28f3f25945 boards: arm: cc3235sf_launchxl: Convert to v2
c3e480f740 boards: arm: cc3220sf_launchxl: Convert to v2
fd5847123f boards: arm: beagleconnect_freedom: Convert to v2
76ba9a0587 boards: arm: cc1352p1_launchxl: Convert to v2
719baa8850 boards: arm: cc1352r1_launchxl: Convert to v2
5060a61ae1 boards: arm: cc1352r_sensortag: Convert to v2
99584be1c5 boards: arm: cc26x2r1_launchxl: Convert to v2
2dc8933942 soc: ti_simplelink: Port to HWMv2
a5b004663b scripts/utils/board_v1_to_v2.py: couple of fixes
77c2c333e5 boards: move 96b_stm32_sensor_mez to 96boards
c14ff98650 boards: stm32f411e_disco: delete obsolete file
bcdc268ccf boards: Convert stm32mp157c_dk2 to HWM v2
0c8ba92e1f boards: Convert 96b_avenger96 to HWM v2
b54fe33077 soc: v2: stm32: Migrate STM32MP1 series
2ba3639b2a boards: Convert nucleo_c031c6 to HWM v2
dbc5ed79f5 soc: st: stm32: Migrate STM32C0 series
ce6d493aa3 boards: Convert stm32l1_disco to HWM v2
a28086a9ca boards: Convert nucleo_l152re to HWM v2
1b2a511d06 boards: Convert 96b_wistrio to HWM v2
ce281f09ab soc: v2: stm32: Migrate STM32L1 series
cdb5364fd7 boards: Convert stm32f769i_disco to HWM v2
768f173dcb boards: Convert stm32f7508_dk to HWM v2
21bbbbd9cb boards: Convert stm32f746g_disco to HWM v2
bab4265693 boards: Convert stm32f723e_disco to HWM v2
58f8fe82ba boards: Convert nucleo_f767zi to HWM v2
37e9084070 boards: Convert nucleo_f756zg to HWM v2
d467e7053a boards: Convert nucleo_f746zg to HWM v2
5f2808d7cc boards: Convert nucleo_f722ze to HWM v2
bbb73e7550 soc: st: Migrate stm32f7 series to new hw model
e9094afc4d soc: st: stm32: stm32f4: change SOC_STM32F405XG to
SOC_STM32F405XX
a1712cdd53 boards: Convert stm32f4_disco to HWM v2
5be404b365 boards: Convert stm32f469i_disco to HWM v2
baaa697ab2 boards: Convert stm32f429i_disc1 to HWM v2
69ecab3c90 boards: Convert stm32f412g_disco to HWM v2
2a572e3fb0 boards: Convert stm32f411e_disco to HWM v2
ecfbf42757 boards: Convert stm32f401_mini to HWM v2
e0191d03bb boards: Convert steval_fcu001v1 to HWM v2
4454648976 boards: Convert segger_trb_stm32f407 to HWM v2
f0ad6ee6b8 boards: Convert olimex_stm32_p405 to HWM v2
1f5e228ec8 boards: Convert olimex_stm32_h407 to HWM v2
834bdb615e boards: Convert olimex_stm32_h405 to HWM v2
8f27fa8de2 boards: Convert olimex_stm32_e407 to HWM v2
f8633a9038 boards: Convert nucleo_f446ze to HWM v2
07e0bd2c07 boards: Convert nucleo_f446re to HWM v2
24d7f625dc boards: Convert nucleo_f429zi to HWM v2
157a8cde53 boards: Convert nucleo_f413zh to HWM v2
4ec99c31b0 boards: Convert nucleo_f412zg to HWM v2
a21546140a boards: Convert nucleo_f411re to HWM v2
43f01ab6de boards: Convert nucleo_f410rb to HWM v2
60c16bcb8b boards: Convert nucleo_f401re to HWM v2
2db228d730 boards: Convert mikroe_mini_m4_for_stm32 to HWM v2
73fc26225c boards: Convert mikroe_clicker_2 to HWM v2
6b62d90114 boards: Convert google_dragonclaw to HWM v2
fa845af309 boards: Convert blackpill_f411ce to HWM v2
5c8c3c3be0 boards: Convert blackpill_f401ce to HWM v2
3c02db1290 boards: Convert blackpill_f401cc to HWM v2
7eeb723cb7 boards: Convert black_f407zg_pro to HWM v2
4f9461d068 boards: Convert black_f407ve to HWM v2
a821de8532 boards: Convert az3166_iotdevkit to HWM v2
ba580c7236 boards: Convert adi_sdp_k1 to HWM v2
eb272ddf19 boards: Convert adafruit_feather_stm32f405 to HWM v2
58ed121c3a boards: Convert 96b_stm32_sensor_mez to HWM v2
b0d70959d3 boards: Convert 96b_neonkey to HWM v2
b1088baadc boards: Convert 96b_carbon to HWM v2
18d867b0a9 boards: Convert 96b_argonkey to HWM v2
ee6ede7119 boards: Convert 96b_aerocore2 to HWM v2
b48e70ead9 soc: v2: stm32: Migrate STM32F4 series
14d2b955da cmake: convert path to CMake style before writing Kconfig
files
9c4ac6a202 boards: posix: bsim: Update paths
14b57f56d7 tests: drivers: gpio: gpio_ite_it8xxx2_v2: Temp fix
f3b173be18 scripts: board_v1_to_v2: Update following move to
boards_legacy
05b50f6691 cmake: CMake soc dir variable improvements for HWMv2
a188e01a12 hwmv2: move all ported boards and socs to their final
location
22c53e97b5 hwmv2: move all non-ported legacy boards and socs to
legacy folders
53f3b181b0 soc: ti_k3: Port to HWMv2
9f19a2075a soc: rk3568: Port to HWMv2
b8928b1628 soc: rk3399: Port to HWMv2
cda3a74868 boards: arm64: qemu_kvm_arm64: Convert to v2
70d704bd20 soc: x86: atom: move and convert to HWMv2
4789e1068e boards: x86: intel_rpl: move and convert raptor_lake
boards to HWMv2
384307e3dc soc: x86: raptor_lake: move and convert to HWMv2
ed025df674 boards: x86: intel_ehl: move and convert elkhart_lake
boards to HWMv2
994b6e1731 soc: x86: elkhart_lake: move and convert to HWMv2
73b30a04cf boards: x86: up_squared_pro_7000: move and convert to
HWMv2
83b133c207 boards: x86: intel_adl: move and convert alder_lake
boards to HWMv2
847a12f1e4 soc: alder_lake: move and convert to HWMv2
67f4c8d2a1 samples: up_squared: adjust gpio_counter to HWMv2
5326b5bfc0 boards: x86: up_squared: move and convert to HWMv2
cfd5e691b4 soc: apollo_lake: move and convert to HWMv2
ac9c235741 boards: xtensa: qemu_xtensa: Convert to v2
f198c3a761 ci: update to osource for soc/Kconfig.defconfig files
e438e6cad4 ci: add SOC_SERIES_ as false positive in
check_compliance.py
95e34da7c1 soc: v2: Convert st_stm32 to st/stm32
313717df76 soc: mps3: Fix missing family
392c3969ed boards: arm: am62x_m4: Convert to v2
8f245d764d tests: Update board names for hwmv2
8f71bb7b4f boards: arm64: khadas_edgev: Convert to v2
e27d23aad0 soc: rk3399: Port to HWMv2
80823b860e boards: arm64: roc_rk3568_pc: Convert to v2
72e4483dec soc: rk3568: Port to HWMv2
bed94669e3 boards: arm64: phycore_am62x_a53: Convert to v2
c01af5a7b8 soc: ti_k3: Port to HWMv2
1e563b4ca3 boards: arm64: xenvm: Convert to v2
76e484adae soc: xenvm: Port to HWMv2
34412f7fe2 boards: arm64: rpi_4b: Convert to v2
9be50e2ca9 soc: bcm2711: Port to HWMv2
bbbed12c2f boards: arm64: qemu_kvm_arm64: Convert to v2
4f5ec7ff8f soc: qemu_virt_arm64: Port to HWMv2
d8d1b9f200 boards: arm64: qemu_cortex_a53: Convert to v2
30bd34b31e soc: qemu_cortex_a53: Port to HWMv2
c20d0dcbb6 boards: arm64: fvp_baser_aemv8r: Convert to v2
02ed6af463 boards: arm64: fvp_base_revc_2xaemv8a: Convert to v2
1b175003a4 soc: fvp_aemv8*: Port to HWMv2
de231b911d boards: v2: Clean up obsolete comments
aa9597f6d9 boards: Convert waveshare_open103z to HWM v2
9644828c81 boards: Convert stm32vl_disco to HWM v2
86ab2bd430 boards: Convert stm32_min_dev to HWM v2
d88d3ddcc4 boards: Convert stm32f103_mini to HWM v2
0ccc0204e1 boards: Convert stm3210c_eval to HWM v2
dd9972d782 boards: Convert olimex_stm32_h103 to HWM v2
a2c2e1406d boards: Convert olimexino_stm32 to HWM v2
2d9c62e118 boards: Convert nucleo_f103rb to HWM v2
e8ba99dc59 soc: v2: stm32: Migrate STM32F1 series
9a93916604 tests: Update board names for hwmv2
9c4d94844d boards: arm: bcm958401m2: Convert to v2
feaf4ffba1 boards: arm: bcm958402m2: Convert to v2
87f0827121 soc: bcm_vk: Port to HWMv2
4526be24a5 boards: arm: quick_feather: Convert to v2
cd921d2b97 boards: arm: qomu: Convert to v2
b3c04051fc soc: quicklogic_eos_s3: Port to HWMv2
a73a9e7533 boards: v2: Clean up obsolete comments
8d87bcc167 boards: Convert stm32f0_disco to HWM v2
1933585785 boards: Convert stm32f072_eval to HWM v2
6f9fe5429d boards: Convert stm32f072b_disco to HWM v2
9dc78e4025 boards: Convert stm32f030_demo to HWM v2
35113e8923 boards: Convert nucleo_f091rc to HWM v2
b276aee9a4 boards: Convert nucleo_f070rb to HWM v2
795f8d611b boards: Convert nucleo_f042k6 to HWM v2
2d82646443 boards: Convert nucleo_f031k6 to HWM v2
959786f12d boards: Convert nucleo_f030r8 to HWM v2
81670db2e9 boards: Convert legend to HWM v2
8980430aad boards: Convert google_kukui to HWM v2
ac020f66e0 dts: stm32f0: fix few warnings
5140e4551a boards: v2: doc: Add vendors
77d640e0c9 soc: v2: stm32: Migrate STM32F0 series
0131e1c159 soc: v2: Add st_stm32 structure and common folder
36b63787a7 boards: v2: Add documentation index for converted boards
ae02fc5047 boards: sparc: qemu_leon3: Convert to v2
f38f7bb223 boards: sparc: gr716a: Convert to v2
d3cca3580e soc: gr716a: Port to HWMv2
6a8a0c1647 boards: sparc: generic_leon3: Convert to v2
faf22185ce soc: leon3: Port to HWMv2
e94762ecdc tests: Update board names for hwmv2
9afcc27e05 boards: xtensa: qemu_xtensa: Convert to v2
3e4a17018f soc: dc233c: Port to HWMv2
9188fdcd78 boards: xtensa: xt-sim: Convert to v2
fcaa41cb5d soc: xtensa_sample_controller: Port to HWMv2
dbc413f7f7 scripts: board_v1_to_v2: Fix CONFIG_SOC_SERIES_ exclusion
6be3d4bc80 kconfig: remove Kconfig BOARD_RPI_PICO_W safe guard.
f4442fa698 boards: v2: Add documentation index for converted boards
ec5fbd67f7 boards: nios2: qemu_nios2: Convert to v2
d3ef220460 soc: nios2-qemu: Port to HWMv2
a223f284b5 boards: nios2: altera_max10: Convert to v2
c381edcb73 soc: nios2f-zephyr: Port to HWMv2
97401c7d2a boards: mips: qemu_malta: Convert to v2
e7a3243a24 soc: qemu_malta: Port to HWMv2
bec82c690d boards: v2: Add documentation index for converted boards
94f6f9b636 boards: arm: w5500_evb_pico: Convert to v2
209235ab6e boards: arm: sparkfun_pro_micro_rp2040: Convert to v2
e5b1885907 boards: arm: adafruit_qt_py_rp2040: Convert to v2
4c750818f9 boards: arm: adafruit_kb2040: Convert to v2
8d3896caa4 boards: arm: rpi_pico: Convert to v2
42cff42c42 soc: rpi_pico: Port to HWMv2
c2df4ca9cb scripts: improve yaml schema and board.yml validation for
revisions
3970f90f71 cmake: clear BOARD_CACHE when invalid board identifier is
given
3a70ee9ccd cmake: improve board revision handling
3cda715fae scripts: board_v1_to_v2: Don't add select
CONFIG_SOC_SERIES_FOO
dc56a543f3 scripts: board_v1_to_v2: Add License + copyright
87147f88c4 cmake: prefer cache BOARD_IDENTIFIER over extracting from
BOARD
65f5dc5b8c cmake: fail when board identifier is applied in legacy hw
model
7db2b6efd8 cmake: cache BOARD_IDENTIFIER to preserve it between
CMake invocations
85dddac5a2 scripts: using extend in list_boards for variant list
6ae5c4e7fd scripts: utils: add board v1->v2 conversion utility
ef834a12d0 maintainers: update Renesas RZT2M path
3ab7830625 boards: renesas: add documentation entry
a0c2ca0491 boards: arm: add documentation entry
27ff3654b7 boards: gigadevice: add documentation entry
6e02f43c0a maintainers: update GD32 paths
1bfcf1d974 boards: gd32l233r_eval: convert to HWMv2
6e621ee43f boards: gd32f470i_eval: convert to HWMv2
219b149768 boards: gd32f450z_eval: convert to HWMv2
91c52b0d39 boards: gd32f450v_start: convert to HWMv2
f0e0a973f6 boards: gd32f407v_start: convert to HWMv2
6f592b64c9 boards: gd32f403z_eval: convert to HWMv2
4bcb4b2ac8 boards: gd32f350r_eval: convert to HWMv2
fdc7ed6eb0 boards: gd32e507z_eval: convert to HWMv2
770376250d boards: gd32e507v_start: convert to HWMv2
a6d8b92e86 boards: gd32e103v_eval: convert to HWMv2
a5f8e5daa1 boards: gd32a503v_eval: convert to HWMv2
5ee799cc5f boards: gd32f450i_eval: convert to HWMv2
8aa8ce4ac8 soc: gigadevice: port to HWMv2
4e203c14c7 cmake: enhanced board entry file handling
312265ee04 scripts: make SoC field mandatory in board.yml
c12ae3bcbc boards: update Renesas rzt2m board.yml to contain SoC
information
c5321c1dbe cmake: make SoC optional for boards containing a single
SoC
bcc06c60ae scripts: support SoC list output for boards
db9e46010c twister: update testcase.yaml and sample.yaml to
mps3/an547 identifier
a988adee7d boards: update arm mps3 an547 board to HWMv2 scheme
7dc2c9db0c soc: use HWMv2 for arm mps3 SoC
c506675b7c boards: update Renesas Starter Kit+ for RZ/T2M board to
HWMv2 scheme
3abb792073 soc: use HWMv2 for renesas_rzt2m SoC
4f52bc646e cmake: support hw model v2 in arch/Kconfig tree
a712b5005b scripts: extend kconfig compliance to verify board / SoC
scheme v2
baa55141a1 twister: update twister testplan.py to handle HWMv2
boards
1f026f70eb boards: extend list_boards.py and update boards CMake
module
bd854a3af8 cmake: introduce arch and soc cmake modules for hw model
v2
c9edefa8fd arch: add existing archs to archs.yml for HWMv2 support
61bbfb5ba2 scripts: introduce list_hardware.py for listing of
architectures and SoCs
a4d1980c35 build: board/ soc: introduce hw model v2 scheme
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
Signed-off-by: David Leach <david.leach@nxp.com>
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This commit is contained in:
Torsten Rasmussen
Anas Nashif
parent
418b0a1e65
commit
8dc3f85622
13315 changed files with 159282 additions and 157416 deletions
4
soc/nuvoton/npcx/CMakeLists.txt
Normal file
4
soc/nuvoton/npcx/CMakeLists.txt
Normal file
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@ -0,0 +1,4 @@
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# SPDX-License-Identifier: Apache-2.0
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add_subdirectory(common)
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add_subdirectory(${SOC_SERIES})
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189
soc/nuvoton/npcx/Kconfig
Normal file
189
soc/nuvoton/npcx/Kconfig
Normal file
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@ -0,0 +1,189 @@
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# Nuvoton Cortex-M4 Embedded Controller
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# Copyright (c) 2020 Nuvoton Technology Corporation.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_FAMILY_NPCX
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menuconfig NPCX_HEADER
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bool "The output binary with NPCX binary header"
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help
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On NPCX series chip, the NPCX ROM code loads firmware image from flash
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to RAM by the firmware binary header setting. Enable this to invoke
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the 'ecst' which generates the NPCX firmware header.
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if NPCX_HEADER
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config NPCX_IMAGE_OUTPUT_BIN
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bool "Build npcx binary in BIN format"
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default y
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help
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Build a "raw" binary zephyr/zephyr.npcx.bin in the build directory.
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The name of this file can be customized with CONFIG_KERNEL_BIN_NAME.
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config NPCX_IMAGE_OUTPUT_HEX
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bool "Build npcx binary in HEX format"
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depends on NPCX_IMAGE_OUTPUT_BIN
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help
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Build an HEX binary zephyr/zephyr.npcx.hex in the build directory.
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||||
This is generated from the npcx BIN image.
|
||||
The name of this file can be customized with CONFIG_KERNEL_BIN_NAME.
|
||||
|
||||
config NPCX_HEADER_CHIP
|
||||
string
|
||||
default "npcx7m6" if SOC_NPCX7M6FB || SOC_NPCX7M6FC
|
||||
default "npcx7m7" if SOC_NPCX7M7FC
|
||||
default "npcx9m3" if SOC_NPCX9M3F
|
||||
default "npcx9m6" if SOC_NPCX9M6F
|
||||
default "npcx9m7" if SOC_NPCX9M7F
|
||||
default "npcx9mfp" if SOC_NPCX9MFP
|
||||
default "npcx4m3" if SOC_NPCX4M3F
|
||||
default "npcx4m8" if SOC_NPCX4M8F
|
||||
|
||||
choice NPCX_HEADER_SPI_MAX_CLOCK_CHOICE
|
||||
prompt "Clock rate to use for SPI flash"
|
||||
default NPCX_HEADER_SPI_MAX_CLOCK_20
|
||||
help
|
||||
This selects the max clock rate that will be used for loading firmware
|
||||
binary from flash to RAM.
|
||||
|
||||
config NPCX_HEADER_SPI_MAX_CLOCK_20
|
||||
bool "SPI flash max clock rate of 20 MHz"
|
||||
|
||||
config NPCX_HEADER_SPI_MAX_CLOCK_25
|
||||
bool "SPI flash max clock rate of 25 MHz"
|
||||
|
||||
config NPCX_HEADER_SPI_MAX_CLOCK_33
|
||||
bool "SPI flash max clock rate of 33 MHz"
|
||||
depends on !SOC_SERIES_NPCX9
|
||||
|
||||
config NPCX_HEADER_SPI_MAX_CLOCK_40
|
||||
bool "SPI flash max clock rate of 40 MHz"
|
||||
|
||||
config NPCX_HEADER_SPI_MAX_CLOCK_50
|
||||
bool "SPI flash max clock rate of 50 MHz"
|
||||
endchoice
|
||||
|
||||
config NPCX_HEADER_SPI_MAX_CLOCK
|
||||
int
|
||||
default 20 if NPCX_HEADER_SPI_MAX_CLOCK_20
|
||||
default 25 if NPCX_HEADER_SPI_MAX_CLOCK_25
|
||||
default 33 if NPCX_HEADER_SPI_MAX_CLOCK_33
|
||||
default 40 if NPCX_HEADER_SPI_MAX_CLOCK_40
|
||||
default 50 if NPCX_HEADER_SPI_MAX_CLOCK_50
|
||||
|
||||
choice NPCX_HEADER_SPI_READ_MODE_CHOICE
|
||||
prompt "Reading mode used by the SPI flash"
|
||||
default NPCX_HEADER_SPI_READ_MODE_NORMAL
|
||||
help
|
||||
This sets the reading mode that can be used by the SPI flash.
|
||||
Reading modes supported are normal, fast, dual, and quad.
|
||||
|
||||
config NPCX_HEADER_SPI_READ_MODE_NORMAL
|
||||
bool "SPI flash operates with normal reading mode"
|
||||
|
||||
config NPCX_HEADER_SPI_READ_MODE_FAST
|
||||
bool "SPI flash operates with fast reading mode"
|
||||
|
||||
config NPCX_HEADER_SPI_READ_MODE_DUAL
|
||||
bool "SPI flash operates with dual reading mode"
|
||||
|
||||
config NPCX_HEADER_SPI_READ_MODE_QUAD
|
||||
bool "SPI flash operates with quad reading mode"
|
||||
endchoice
|
||||
|
||||
config NPCX_HEADER_SPI_READ_MODE
|
||||
string
|
||||
default "normal" if NPCX_HEADER_SPI_READ_MODE_NORMAL
|
||||
default "fast" if NPCX_HEADER_SPI_READ_MODE_FAST
|
||||
default "dual" if NPCX_HEADER_SPI_READ_MODE_DUAL
|
||||
default "quad" if NPCX_HEADER_SPI_READ_MODE_QUAD
|
||||
|
||||
choice NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_CHOICE
|
||||
prompt "Core clock to SPI flash clock ratio"
|
||||
default NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1
|
||||
help
|
||||
This sets the clock ratio (core clock / SPI clock)
|
||||
|
||||
config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1
|
||||
bool "NPCX SPI clock ratio 1"
|
||||
help
|
||||
The SPI flash clock has the same frequency as the core clock.
|
||||
|
||||
config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2
|
||||
bool "NPCX SPI clock ratio 2"
|
||||
help
|
||||
The core clock frequency is twice the flash clock frequency.
|
||||
endchoice
|
||||
|
||||
config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO
|
||||
int
|
||||
default 1 if NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1
|
||||
default 2 if NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2
|
||||
|
||||
config NPCX_HEADER_ENABLE_HEADER_CRC
|
||||
bool "Header crc check"
|
||||
help
|
||||
When enabled, the header will be verified at boot using a crc
|
||||
checksum.
|
||||
|
||||
config NPCX_HEADER_ENABLE_FIRMWARE_CRC
|
||||
bool "Firmware image crc check"
|
||||
help
|
||||
When enabled, the firmware image will be verified at boot using a
|
||||
crc checksum.
|
||||
|
||||
choice NPCX_HEADER_FLASH_SIZE_CHOICE
|
||||
prompt "Flash size"
|
||||
default NPCX_HEADER_FLASH_SIZE_0P5M_1M if SOC_SERIES_NPCX7 || \
|
||||
SOC_SERIES_NPCX9
|
||||
default NPCX_HEADER_FLASH_SIZE_16M
|
||||
help
|
||||
This sets the SPI flash size.
|
||||
|
||||
config NPCX_HEADER_FLASH_SIZE_0P5M_1M
|
||||
bool "SPI flash size 0.5M or 1M Bytes"
|
||||
help
|
||||
The SPI flash size is 0.5M or 1M Bytes.
|
||||
|
||||
config NPCX_HEADER_FLASH_SIZE_2M
|
||||
bool "SPI flash size 2M Bytes"
|
||||
help
|
||||
The SPI flash size is 2M Bytes.
|
||||
|
||||
config NPCX_HEADER_FLASH_SIZE_4M
|
||||
bool "SPI flash size 4M Bytes"
|
||||
help
|
||||
The SPI flash size is 4M Bytes.
|
||||
|
||||
config NPCX_HEADER_FLASH_SIZE_8M
|
||||
bool "SPI flash size 8M Bytes"
|
||||
help
|
||||
The SPI flash size is 8M Bytes.
|
||||
|
||||
config NPCX_HEADER_FLASH_SIZE_16M
|
||||
bool "SPI flash size 16M Bytes"
|
||||
help
|
||||
The SPI flash size is 16M Bytes.
|
||||
endchoice
|
||||
|
||||
config NPCX_HEADER_FLASH_SIZE
|
||||
int
|
||||
default 1 if NPCX_HEADER_FLASH_SIZE_0P5M_1M
|
||||
default 2 if NPCX_HEADER_FLASH_SIZE_2M
|
||||
default 4 if NPCX_HEADER_FLASH_SIZE_4M
|
||||
default 8 if NPCX_HEADER_FLASH_SIZE_8M
|
||||
default 16 if NPCX_HEADER_FLASH_SIZE_16M
|
||||
|
||||
endif # NPCX_HEADER
|
||||
|
||||
config NPCX_PM_TRACE
|
||||
bool "Trace System Power Management in NPCX family"
|
||||
depends on PM
|
||||
help
|
||||
Internal config to enable runtime power management traces.
|
||||
|
||||
endif # SOC_FAMILY_NPCX
|
||||
|
||||
# Select SoC Part No. and configuration options
|
||||
rsource "*/Kconfig"
|
||||
10
soc/nuvoton/npcx/Kconfig.defconfig
Normal file
10
soc/nuvoton/npcx/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# Copyright (c) 2020 Nuvoton Technology Corporation.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_FAMILY_NPCX
|
||||
|
||||
rsource "*/Kconfig.defconfig"
|
||||
|
||||
endif # SOC_FAMILY_NPCX
|
||||
12
soc/nuvoton/npcx/Kconfig.soc
Normal file
12
soc/nuvoton/npcx/Kconfig.soc
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
# Nuvoton Cortex-M4 Embedded Controller
|
||||
|
||||
# Copyright (c) 2020 Nuvoton Technology Corporation.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_FAMILY_NPCX
|
||||
bool
|
||||
|
||||
config SOC_FAMILY
|
||||
default "nuvoton_npcx" if SOC_FAMILY_NPCX
|
||||
|
||||
rsource "*/Kconfig.soc"
|
||||
48
soc/nuvoton/npcx/common/CMakeLists.txt
Normal file
48
soc/nuvoton/npcx/common/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_include_directories(.)
|
||||
zephyr_sources_ifdef(CONFIG_PM power.c)
|
||||
zephyr_sources(
|
||||
scfg.c
|
||||
registers.c
|
||||
)
|
||||
|
||||
# Check for disabling header CRC.
|
||||
if (NOT DEFINED CONFIG_NPCX_HEADER_ENABLE_HEADER_CRC)
|
||||
set(NPCX_HEADER_HCRC "-nohcrc")
|
||||
endif()
|
||||
|
||||
# Check for disabling firmware CRC.
|
||||
if (NOT DEFINED CONFIG_NPCX_HEADER_ENABLE_FIRMWARE_CRC)
|
||||
set(NPCX_HEADER_FCRC "-nofcrc")
|
||||
endif()
|
||||
|
||||
if (DEFINED CONFIG_NPCX_IMAGE_OUTPUT_BIN)
|
||||
set(NPCX_BIN_NAME ${CONFIG_KERNEL_BIN_NAME}.npcx.bin)
|
||||
string(TOUPPER "${SOC_NAME}" soc_name_upper)
|
||||
set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
|
||||
COMMAND ${PYTHON_EXECUTABLE} ${SOC_${soc_name_upper}_DIR}/common/ecst/ecst.py
|
||||
-i ${KERNEL_BIN_NAME}
|
||||
-o ${NPCX_BIN_NAME}
|
||||
${NPCX_HEADER_HCRC} ${NPCX_HEADER_FCRC}
|
||||
-chip ${CONFIG_NPCX_HEADER_CHIP}
|
||||
-flashsize ${CONFIG_NPCX_HEADER_FLASH_SIZE}
|
||||
-spiclkratio ${CONFIG_NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO}
|
||||
-spimaxclk ${CONFIG_NPCX_HEADER_SPI_MAX_CLOCK}
|
||||
-spireadmode ${CONFIG_NPCX_HEADER_SPI_READ_MODE}
|
||||
)
|
||||
if (DEFINED CONFIG_NPCX_IMAGE_OUTPUT_HEX)
|
||||
set(NPCX_HEX_NAME ${CONFIG_KERNEL_BIN_NAME}.npcx.hex)
|
||||
# Property magic which makes west flash choose right file.
|
||||
set_property(TARGET runners_yaml_props_target PROPERTY hex_file "${CONFIG_KERNEL_BIN_NAME}.npcx.hex")
|
||||
set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
|
||||
COMMAND $<TARGET_PROPERTY:bintools,elfconvert_command>
|
||||
$<TARGET_PROPERTY:bintools,elfconvert_flag>
|
||||
$<TARGET_PROPERTY:bintools,elfconvert_flag_intarget>binary
|
||||
$<TARGET_PROPERTY:bintools,elfconvert_flag_outtarget>ihex
|
||||
$<TARGET_PROPERTY:bintools,elfconvert_flag_infile>${NPCX_BIN_NAME}
|
||||
$<TARGET_PROPERTY:bintools,elfconvert_flag_outfile>${NPCX_HEX_NAME}
|
||||
$<TARGET_PROPERTY:bintools,elfconvert_flag_final>
|
||||
)
|
||||
endif()
|
||||
endif()
|
||||
1004
soc/nuvoton/npcx/common/ecst/ecst.py
Executable file
1004
soc/nuvoton/npcx/common/ecst/ecst.py
Executable file
File diff suppressed because it is too large
Load diff
252
soc/nuvoton/npcx/common/ecst/ecst_args.py
Executable file
252
soc/nuvoton/npcx/common/ecst/ecst_args.py
Executable file
|
|
@ -0,0 +1,252 @@
|
|||
#!/usr/bin/env python3
|
||||
#
|
||||
# Copyright (c) 2020 Nuvoton Technology Corporation
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# This file contains general functions for ECST application
|
||||
|
||||
import sys
|
||||
import argparse
|
||||
import colorama
|
||||
from colorama import Fore
|
||||
|
||||
INVALID_INPUT = -1
|
||||
EXIT_FAILURE_STATUS = 1
|
||||
|
||||
# Header common fields
|
||||
FW_HDR_CRC_DISABLE = 0x00
|
||||
FW_HDR_CRC_ENABLE = 0x02
|
||||
FW_CRC_DISABLE = 0x00
|
||||
FW_CRC_ENABLE = 0x02
|
||||
|
||||
SPI_CLOCK_RATIO_1 = 0x00
|
||||
SPI_CLOCK_RATIO_2 = 0x08
|
||||
|
||||
SPI_UNLIMITED_BURST_DISABLE = 0x00
|
||||
SPI_UNLIMITED_BURST_ENABLE = 0x08
|
||||
|
||||
# Verbose related values
|
||||
NO_VERBOSE = 0
|
||||
REG_VERBOSE = 1
|
||||
SUPER_VERBOSE = 1
|
||||
|
||||
# argument default values.
|
||||
DEFAULT_MODE = "bt"
|
||||
SPI_MAX_CLOCK_DEFAULT = "20"
|
||||
FLASH_SIZE_DEFAULT = "16"
|
||||
SPI_CLOCK_RATIO_DEFAULT = 1
|
||||
PASTE_FIRMWARE_HEADER_DEFAULT = 0x00000000
|
||||
DEFAULT_VERBOSE = NO_VERBOSE
|
||||
SPI_MODE_VAL_DEFAULT = 'normal'
|
||||
SPI_UNLIMITED_BURST_DEFAULT = SPI_UNLIMITED_BURST_DISABLE
|
||||
FW_HDR_CRC_DEFAULT = FW_HDR_CRC_ENABLE
|
||||
FW_CRC_DEFAULT = FW_CRC_ENABLE
|
||||
FW_CRC_START_OFFSET_DEFAULT = 0x0
|
||||
POINTER_OFFSET_DEFAULT = 0x0
|
||||
|
||||
# Chips: convert from name to index.
|
||||
CHIPS_INFO = {
|
||||
'npcx7m5': {'ram_address': 0x100a8000, 'ram_size': 0x20000},
|
||||
'npcx7m6': {'ram_address': 0x10090000, 'ram_size': 0x40000},
|
||||
'npcx7m7': {'ram_address': 0x10070000, 'ram_size': 0x60000},
|
||||
'npcx9m3': {'ram_address': 0x10080000, 'ram_size': 0x50000},
|
||||
'npcx9m6': {'ram_address': 0x10090000, 'ram_size': 0x40000},
|
||||
'npcx9m7': {'ram_address': 0x10070000, 'ram_size': 0x60000},
|
||||
'npcx9mfp': {'ram_address': 0x10058000, 'ram_size': 0x80000},
|
||||
'npcx4m3': {'ram_address': 0x10088000, 'ram_size': 0x50000},
|
||||
'npcx4m8': {'ram_address': 0x10060000, 'ram_size': 0x7c800},
|
||||
}
|
||||
DEFAULT_CHIP = 'npcx7m6'
|
||||
|
||||
# RAM related values
|
||||
RAM_ADDR = 0x00
|
||||
RAM_SIZE = 0x01
|
||||
|
||||
class EcstArgs:
|
||||
"""creates an arguments object for the ECST,
|
||||
the arguments are taken from the command line and/or
|
||||
argument file
|
||||
"""
|
||||
error_args = None
|
||||
|
||||
mode = DEFAULT_MODE
|
||||
help = False
|
||||
verbose = DEFAULT_VERBOSE
|
||||
super_verbose = False
|
||||
input = None
|
||||
output = None
|
||||
args_file = None
|
||||
chip_name = DEFAULT_CHIP
|
||||
chip_ram_address = CHIPS_INFO[DEFAULT_CHIP]['ram_address']
|
||||
chip_ram_size = CHIPS_INFO[DEFAULT_CHIP]['ram_address']
|
||||
firmware_header_crc = FW_HDR_CRC_DEFAULT
|
||||
firmware_crc = FW_CRC_DEFAULT
|
||||
spi_flash_maximum_clock = SPI_MAX_CLOCK_DEFAULT
|
||||
spi_flash_clock_ratio = SPI_CLOCK_RATIO_DEFAULT
|
||||
unlimited_burst_mode = SPI_UNLIMITED_BURST_DEFAULT
|
||||
spi_flash_read_mode = SPI_MODE_VAL_DEFAULT
|
||||
firmware_load_address = None
|
||||
firmware_entry_point = None
|
||||
use_arm_reset = True
|
||||
firmware_crc_start = FW_CRC_START_OFFSET_DEFAULT
|
||||
firmware_crc_size = None
|
||||
firmware_length = None
|
||||
flash_size = FLASH_SIZE_DEFAULT
|
||||
paste_firmware_header = PASTE_FIRMWARE_HEADER_DEFAULT
|
||||
pointer = POINTER_OFFSET_DEFAULT
|
||||
bh_offset = None
|
||||
|
||||
def __init__(self):
|
||||
|
||||
arguments = _create_parser("")
|
||||
valid_arguments = arguments[0]
|
||||
invalid_arguments = arguments[1]
|
||||
self.error_args = invalid_arguments
|
||||
|
||||
_populate_args(self, valid_arguments)
|
||||
_populate_chip_fields(self)
|
||||
|
||||
def _populate_chip_fields(self):
|
||||
"""populate the chip related fields for the ecst"""
|
||||
self.chip_name = self.chip_name
|
||||
chip = str(self.chip_name).lower()
|
||||
|
||||
if chip not in CHIPS_INFO:
|
||||
self.chip_name = INVALID_INPUT
|
||||
return
|
||||
|
||||
self.chip_ram_address = CHIPS_INFO[chip]['ram_address']
|
||||
self.chip_ram_size = CHIPS_INFO[chip]['ram_size']
|
||||
if self.firmware_load_address is None:
|
||||
self.firmware_load_address = self.chip_ram_address
|
||||
|
||||
def _populate_args(self, argument_list):
|
||||
"""populate the ecst arguments according to the command line/ args file"""
|
||||
for arg in vars(argument_list):
|
||||
if (arg == "input") & (argument_list.input is not None):
|
||||
self.input = argument_list.input
|
||||
|
||||
elif (arg == "output") & (argument_list.output is not None):
|
||||
self.output = argument_list.output
|
||||
|
||||
elif (arg == "chip") & (argument_list.chip is not None):
|
||||
self.chip_name = argument_list.chip
|
||||
_populate_chip_fields(self)
|
||||
|
||||
elif (arg == "verbose") & argument_list.verbose:
|
||||
self.verbose = REG_VERBOSE
|
||||
|
||||
elif (arg == "super_verbose") & argument_list.super_verbose:
|
||||
self.verbose = SUPER_VERBOSE
|
||||
|
||||
elif (arg == "spi_flash_maximum_clock") & \
|
||||
(argument_list.spi_flash_maximum_clock is not None):
|
||||
self.spi_flash_maximum_clock =\
|
||||
argument_list.spi_flash_maximum_clock
|
||||
|
||||
elif (arg == "spi_flash_clock_ratio") & \
|
||||
(argument_list.spi_flash_clock_ratio is not None):
|
||||
if argument_list.spi_flash_clock_ratio.isdigit():
|
||||
self.spi_flash_clock_ratio =\
|
||||
int(argument_list.spi_flash_clock_ratio)
|
||||
else:
|
||||
self.spi_flash_clock_ratio = INVALID_INPUT
|
||||
|
||||
elif (arg == "firmware_header_crc") &\
|
||||
argument_list.firmware_header_crc:
|
||||
self.firmware_header_crc = FW_HDR_CRC_DISABLE
|
||||
|
||||
elif (arg == "firmware_crc") & argument_list.firmware_crc:
|
||||
self.firmware_crc = FW_CRC_DISABLE
|
||||
|
||||
elif (arg == "spi_read_mode") &\
|
||||
(argument_list.spi_read_mode is not None):
|
||||
|
||||
self.spi_flash_read_mode = argument_list.spi_read_mode
|
||||
|
||||
elif (arg == "flash_size") & (argument_list.flash_size is not None):
|
||||
self.flash_size = argument_list.flash_size
|
||||
|
||||
elif (arg == "paste_firmware_header") & \
|
||||
(argument_list.paste_firmware_header is not None):
|
||||
if _is_hex(argument_list.paste_firmware_header):
|
||||
self.paste_firmware_header =\
|
||||
int(argument_list.paste_firmware_header, 16)
|
||||
else:
|
||||
self.paste_firmware_header = INVALID_INPUT
|
||||
|
||||
def _create_parser(arg_list):
|
||||
"""create argument parser according to pre-defined arguments
|
||||
|
||||
:param arg_list: when empty, parses command line arguments,
|
||||
else parses the given string
|
||||
"""
|
||||
|
||||
parser = argparse.ArgumentParser(conflict_handler='resolve', allow_abbrev=False)
|
||||
parser.add_argument("-i", nargs='?', dest="input")
|
||||
parser.add_argument("-o", nargs='?', dest="output")
|
||||
parser.add_argument("-chip", dest="chip")
|
||||
parser.add_argument("-v", action="store_true", dest="verbose")
|
||||
parser.add_argument("-vv", action="store_true", dest="super_verbose")
|
||||
parser.add_argument("-nohcrc", action="store_true",
|
||||
dest="firmware_header_crc")
|
||||
parser.add_argument("-nofcrc", action="store_true", dest="firmware_crc")
|
||||
parser.add_argument("-spimaxclk", nargs='?',
|
||||
dest="spi_flash_maximum_clock")
|
||||
parser.add_argument("-spiclkratio", nargs='?',
|
||||
dest="spi_flash_clock_ratio")
|
||||
parser.add_argument("-spireadmode", nargs='?', dest="spi_read_mode")
|
||||
parser.add_argument("-flashsize", nargs='?', dest="flash_size")
|
||||
parser.add_argument("-ph", nargs='?', dest="paste_firmware_header")
|
||||
|
||||
args = parser.parse_known_args(arg_list.split())
|
||||
|
||||
if arg_list == "":
|
||||
args = parser.parse_known_args()
|
||||
|
||||
return args
|
||||
|
||||
def _file_to_line(arg_file):
|
||||
"""helper to convert a text file to one line string
|
||||
used to parse the arguments in a given argfile
|
||||
|
||||
:param arg_file: the file to manipulate
|
||||
"""
|
||||
with open(arg_file, "r") as arg_file_to_read:
|
||||
data = arg_file_to_read.read().strip()
|
||||
arg_file_to_read.close()
|
||||
|
||||
return data
|
||||
|
||||
def _is_hex(val):
|
||||
"""helper to determine whether an input is a hex
|
||||
formatted number
|
||||
|
||||
:param val: input to be checked
|
||||
"""
|
||||
if val.startswith("0x") or val.startswith("0X"):
|
||||
val = val[2:]
|
||||
hex_digits = set("0123456789abcdefABCDEF")
|
||||
for char in val:
|
||||
if char not in hex_digits:
|
||||
return False
|
||||
return True
|
||||
|
||||
def exit_with_failure(message):
|
||||
"""formatted failure message printer, prints the
|
||||
relevant error message and exits the application.
|
||||
|
||||
:param message: the error message to be printed
|
||||
"""
|
||||
|
||||
message = '\n' + message
|
||||
message += '\n'
|
||||
message += '******************************\n'
|
||||
message += '*** FAILED ***\n'
|
||||
message += '******************************\n'
|
||||
print(Fore.RED + message)
|
||||
|
||||
sys.exit(EXIT_FAILURE_STATUS)
|
||||
|
||||
colorama.init()
|
||||
280
soc/nuvoton/npcx/common/pinctrl_soc.h
Normal file
280
soc/nuvoton/npcx/common/pinctrl_soc.h
Normal file
|
|
@ -0,0 +1,280 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _NUVOTON_PINCTRL_SOC_H_
|
||||
#define _NUVOTON_PINCTRL_SOC_H_
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/sys/util_macro.h>
|
||||
#include <zephyr/types.h>
|
||||
|
||||
/**
|
||||
* @brief Pinctrl node types in NPCX series
|
||||
*/
|
||||
enum npcx_pinctrl_type {
|
||||
NPCX_PINCTRL_TYPE_PERIPH,
|
||||
NPCX_PINCTRL_TYPE_DEVICE_CTRL,
|
||||
NPCX_PINCTRL_TYPE_PSL_IN,
|
||||
NPCX_PINCTRL_TYPE_RESERVED,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Suppoerted peripheral device configuration type in NPCX series
|
||||
*/
|
||||
enum npcx_periph_type {
|
||||
NPCX_PINCTRL_TYPE_PERIPH_PINMUX,
|
||||
NPCX_PINCTRL_TYPE_PERIPH_PUPD,
|
||||
NPCX_PINCTRL_TYPE_PERIPH_DRIVE,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Suppoerted IO bias type in NPCX series
|
||||
*/
|
||||
enum npcx_io_bias_type {
|
||||
NPCX_BIAS_TYPE_NONE,
|
||||
NPCX_BIAS_TYPE_PULL_DOWN,
|
||||
NPCX_BIAS_TYPE_PULL_UP,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Suppoerted IO drive type in NPCX series
|
||||
*/
|
||||
enum npcx_io_drive_type {
|
||||
NPCX_DRIVE_TYPE_PUSH_PULL,
|
||||
NPCX_DRIVE_TYPE_OPEN_DRAIN,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Suppoerted PSL input detection mode in NPCX series
|
||||
*/
|
||||
enum npcx_psl_in_mode {
|
||||
NPCX_PSL_IN_MODE_LEVEL,
|
||||
NPCX_PSL_IN_MODE_EDGE,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Suppoerted PSL input detection polarity in NPCX series
|
||||
*/
|
||||
enum npcx_psl_in_pol {
|
||||
NPCX_PSL_IN_POL_LOW,
|
||||
NPCX_PSL_IN_POL_HIGH,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief NPCX peripheral device configuration structure
|
||||
*
|
||||
* Used to indicate the peripheral device's corresponding register/bit for
|
||||
* pin-muxing, pull-up/down and so on.
|
||||
*/
|
||||
struct npcx_periph {
|
||||
/** Related register group for peripheral device. */
|
||||
uint16_t group: 8;
|
||||
/** Related register bit for peripheral device. */
|
||||
uint16_t bit: 3;
|
||||
/** The polarity for peripheral device functionality. */
|
||||
bool inverted: 1;
|
||||
/** The type of peripheral device configuration. */
|
||||
enum npcx_periph_type type: 2;
|
||||
/** Reserved field. */
|
||||
uint16_t reserved: 2;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* @brief NPCX device control structure
|
||||
*
|
||||
* Used to indicate the device's corresponding register/field for its io
|
||||
* characteristics such as tri-state, power supply type selection, and so on.
|
||||
*/
|
||||
struct npcx_dev_ctl {
|
||||
/** Related register offset for device configuration. */
|
||||
uint16_t offest: 5;
|
||||
/** Related register field offset for device control. */
|
||||
uint16_t field_offset: 3;
|
||||
/** Related register field size for device control. */
|
||||
uint16_t field_size: 3;
|
||||
/** field value */
|
||||
uint16_t field_value: 5;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* @brief NPCX Power Switch Logic (PSL) input pad configuration structure
|
||||
*
|
||||
* Used to indicate a Power Switch Logic (PSL) input detection configuration
|
||||
* such as detection polarity, port number, and so on.
|
||||
*/
|
||||
struct npcx_psl_input {
|
||||
/** Indicate a PSL input port number. */
|
||||
uint16_t port: 5;
|
||||
/** Related register group for detection polarity of PSL input. */
|
||||
uint16_t pol_group: 8;
|
||||
/** Related register bit for detection polarity of PSL input. */
|
||||
uint16_t pol_bit: 3;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* @brief Type for NPCX pin configuration. Please make sure the size of this
|
||||
* structure is 4 bytes in case the impact of ROM usage.
|
||||
*/
|
||||
struct npcx_pinctrl {
|
||||
union {
|
||||
struct npcx_periph periph;
|
||||
struct npcx_dev_ctl dev_ctl;
|
||||
struct npcx_psl_input psl_in;
|
||||
uint16_t cfg_word;
|
||||
} cfg;
|
||||
struct {
|
||||
/** Indicates the current pinctrl type. */
|
||||
enum npcx_pinctrl_type type :2;
|
||||
/** Properties used for pinmuxing. */
|
||||
bool pinmux_lock :1;
|
||||
bool pinmux_gpio :1;
|
||||
/** Properties used for io-pad. */
|
||||
enum npcx_io_bias_type io_bias_type :2;
|
||||
enum npcx_io_drive_type io_drive_type :1;
|
||||
/** Properties used for PSL input. */
|
||||
enum npcx_psl_in_mode psl_in_mode :1;
|
||||
enum npcx_psl_in_pol psl_in_polarity :1;
|
||||
uint16_t reserved :7;
|
||||
} flags;
|
||||
} __packed;
|
||||
|
||||
typedef struct npcx_pinctrl pinctrl_soc_pin_t;
|
||||
|
||||
/** Helper macros for NPCX pinctrl configurations. */
|
||||
#define Z_PINCTRL_NPCX_BIAS_TYPE(node_id) \
|
||||
COND_CODE_1(DT_PROP(node_id, bias_pull_up), (NPCX_BIAS_TYPE_PULL_UP), \
|
||||
(COND_CODE_1(DT_PROP(node_id, bias_pull_down), \
|
||||
(NPCX_BIAS_TYPE_PULL_DOWN), (NPCX_BIAS_TYPE_NONE))))
|
||||
|
||||
#define Z_PINCTRL_NPCX_DRIVE_TYPE(node_id) \
|
||||
COND_CODE_1(DT_PROP(node_id, drive_open_drain), \
|
||||
(NPCX_DRIVE_TYPE_OPEN_DRAIN), (NPCX_DRIVE_TYPE_PUSH_PULL))
|
||||
|
||||
#define Z_PINCTRL_NPCX_HAS_PUPD_PROP(node_id) \
|
||||
UTIL_OR(DT_PROP(node_id, bias_pull_down), \
|
||||
DT_PROP(node_id, bias_pull_up))
|
||||
|
||||
#define Z_PINCTRL_NPCX_HAS_DRIVE_PROP(node_id, node_periph) \
|
||||
UTIL_AND(DT_PROP(node_id, drive_open_drain), \
|
||||
DT_NODE_HAS_PROP(node_periph, pwm_channel))
|
||||
|
||||
#define Z_PINCTRL_NPCX_HAS_PSL_IN_PROP(node_id) \
|
||||
UTIL_AND(DT_NODE_HAS_PROP(node_id, psl_in_pol), \
|
||||
DT_NODE_HAS_PROP(node_id, psl_in_mode))
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize a periphral pinmux configuration.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
* @param prop Property name for pinmux configuration. (i.e. 'pinmux')
|
||||
*/
|
||||
#define Z_PINCTRL_NPCX_PERIPH_PINMUX_INIT(node_id, prop) \
|
||||
{ \
|
||||
.flags.type = NPCX_PINCTRL_TYPE_PERIPH, \
|
||||
.flags.pinmux_lock = DT_PROP(node_id, pinmux_locked), \
|
||||
.flags.pinmux_gpio = DT_PROP(node_id, pinmux_gpio), \
|
||||
.cfg.periph.type = NPCX_PINCTRL_TYPE_PERIPH_PINMUX, \
|
||||
.cfg.periph.group = DT_PHA(DT_PROP(node_id, prop), alts, group), \
|
||||
.cfg.periph.bit = DT_PHA(DT_PROP(node_id, prop), alts, bit), \
|
||||
.cfg.periph.inverted = DT_PHA(DT_PROP(node_id, prop), alts, inv), \
|
||||
},
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize a periphral pinmux configuration.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
* @param prop Property name for pinmux configuration. (i.e. 'pinmux')
|
||||
*/
|
||||
#define Z_PINCTRL_NPCX_DEVICE_CONTROL_INIT(node_id, prop) \
|
||||
{ \
|
||||
.flags.type = NPCX_PINCTRL_TYPE_DEVICE_CTRL, \
|
||||
.cfg.dev_ctl.offest = DT_PROP_BY_IDX(node_id, prop, 0), \
|
||||
.cfg.dev_ctl.field_offset = DT_PROP_BY_IDX(node_id, prop, 1), \
|
||||
.cfg.dev_ctl.field_size = DT_PROP_BY_IDX(node_id, prop, 2), \
|
||||
.cfg.dev_ctl.field_value = DT_PROP_BY_IDX(node_id, prop, 3), \
|
||||
},
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize a periphral pull-up/down configuration.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
* @param prop Property name for pull-up/down configuration. (i.e. 'periph-pupd')
|
||||
*/
|
||||
#define Z_PINCTRL_NPCX_PERIPH_PUPD_INIT(node_id, prop) \
|
||||
{ \
|
||||
.flags.type = NPCX_PINCTRL_TYPE_PERIPH, \
|
||||
.flags.io_bias_type = Z_PINCTRL_NPCX_BIAS_TYPE(node_id), \
|
||||
.cfg.periph.type = NPCX_PINCTRL_TYPE_PERIPH_PUPD, \
|
||||
.cfg.periph.group = DT_PROP_BY_IDX(node_id, prop, 0), \
|
||||
.cfg.periph.bit = DT_PROP_BY_IDX(node_id, prop, 1), \
|
||||
},
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize a periphral drive mode configuration.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
* @param node_periph Peripheral node identifier.
|
||||
*/
|
||||
#define Z_PINCTRL_NPCX_PERIPH_DRIVE_INIT(node_id, node_periph) \
|
||||
{ \
|
||||
.flags.type = NPCX_PINCTRL_TYPE_PERIPH, \
|
||||
.flags.io_drive_type = Z_PINCTRL_NPCX_DRIVE_TYPE(node_id), \
|
||||
.cfg.periph.type = NPCX_PINCTRL_TYPE_PERIPH_DRIVE, \
|
||||
.cfg.periph.group = DT_PROP(node_periph, pwm_channel), \
|
||||
},
|
||||
|
||||
/*
|
||||
* @brief Utility macro to initialize a Power Switch Logic (PSL) input detection
|
||||
* configurations.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
* @param prop Property name for pull-up/down configuration. (i.e. 'polarity')
|
||||
*/
|
||||
#define Z_PINCTRL_NPCX_PSL_IN_DETECT_CONF_INIT(node_id, prop) \
|
||||
{ \
|
||||
.flags.type = NPCX_PINCTRL_TYPE_PSL_IN, \
|
||||
.flags.psl_in_mode = DT_ENUM_IDX(node_id, psl_in_mode), \
|
||||
.flags.psl_in_polarity = DT_ENUM_IDX(node_id, psl_in_pol), \
|
||||
.cfg.psl_in.port = DT_PROP(node_id, psl_offset), \
|
||||
.cfg.psl_in.pol_group = DT_PHA(DT_PROP(node_id, prop), alts, group), \
|
||||
.cfg.psl_in.pol_bit = DT_PHA(DT_PROP(node_id, prop), alts, bit), \
|
||||
},
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize all peripheral confiurations for each pin.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
* @param prop Pinctrl state property name. (i.e. 'pinctrl-0/1/2')
|
||||
* @param idx Property entry index.
|
||||
*/
|
||||
#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
|
||||
COND_CODE_1(Z_PINCTRL_NPCX_HAS_DRIVE_PROP( \
|
||||
DT_PROP_BY_IDX(node_id, prop, idx), node_id), \
|
||||
(Z_PINCTRL_NPCX_PERIPH_DRIVE_INIT( \
|
||||
DT_PROP_BY_IDX(node_id, prop, idx), node_id)), ()) \
|
||||
COND_CODE_1(Z_PINCTRL_NPCX_HAS_PUPD_PROP(DT_PROP_BY_IDX(node_id, prop, idx)), \
|
||||
(Z_PINCTRL_NPCX_PERIPH_PUPD_INIT( \
|
||||
DT_PROP_BY_IDX(node_id, prop, idx), periph_pupd)), ()) \
|
||||
COND_CODE_1(Z_PINCTRL_NPCX_HAS_PSL_IN_PROP(DT_PROP_BY_IDX(node_id, prop, idx)), \
|
||||
(Z_PINCTRL_NPCX_PSL_IN_DETECT_CONF_INIT( \
|
||||
DT_PROP_BY_IDX(node_id, prop, idx), psl_polarity)), ()) \
|
||||
COND_CODE_1(DT_NODE_HAS_PROP(DT_PROP_BY_IDX(node_id, prop, idx), dev_ctl), \
|
||||
(Z_PINCTRL_NPCX_DEVICE_CONTROL_INIT( \
|
||||
DT_PROP_BY_IDX(node_id, prop, idx), dev_ctl)), ()) \
|
||||
COND_CODE_1(DT_NODE_HAS_PROP(DT_PROP_BY_IDX(node_id, prop, idx), pinmux), \
|
||||
(Z_PINCTRL_NPCX_PERIPH_PINMUX_INIT( \
|
||||
DT_PROP_BY_IDX(node_id, prop, idx), pinmux)), ())
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize state pins contained in a given property.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
* @param prop Property name describing state pins.
|
||||
*/
|
||||
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
|
||||
{DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT)}
|
||||
|
||||
#endif /* _NUVOTON_PINCTRL_SOC_H_ */
|
||||
257
soc/nuvoton/npcx/common/power.c
Normal file
257
soc/nuvoton/npcx/common/power.c
Normal file
|
|
@ -0,0 +1,257 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Nuvoton NPCX power management driver
|
||||
*
|
||||
* This file contains the drivers of NPCX Power Manager Modules that improves
|
||||
* the efficiency of ec operation by adjusting the chip’s power consumption to
|
||||
* the level of activity required by the application. The following table
|
||||
* summarizes the main properties of the various power states and shows the
|
||||
* activity levels of the various clocks while in these power states.
|
||||
*
|
||||
* +--------------------------------------------------------------------------+
|
||||
* | Power State | LFCLK | HFCLK | APB/AHB | Core | RAM/Regs | VCC | VSBY |
|
||||
* |--------------------------------------------------------------------------|
|
||||
* | Active | On | On | On | Active | Active | On | On |
|
||||
* | Idle (wfi) | On | On | On | Wait | Active | On | On |
|
||||
* | Sleep | On | On | Stop | Stop | Preserved | On | On |
|
||||
* | Deep Sleep | On | Stop | Stop | Stop | Power Down | On | On |
|
||||
* | Stand-By | Off | Off | Off | Off | Off | Off | On |
|
||||
* +--------------------------------------------------------------------------+
|
||||
*
|
||||
* LFCLK - Low-Frequency Clock. Its frequency is fixed to 32kHz.
|
||||
* HFCLK - High-Frequency (PLL) Clock. Its frequency is configured to OFMCLK.
|
||||
*
|
||||
* Based on the following criteria:
|
||||
*
|
||||
* - A delay of 'Instant' wake-up from 'Deep Sleep' is 20 us.
|
||||
* - A delay of 'Standard' wake-up from 'Deep Sleep' is 3.43 ms.
|
||||
* - Max residency time in Deep Sleep for 'Instant' wake-up is 200 ms
|
||||
* - Min Residency time in Deep Sleep for 'Instant' wake-up is 61 us
|
||||
* - The unit to determine power state residency policy is tick.
|
||||
*
|
||||
* this driver implements one power state, PM_STATE_SUSPEND_TO_IDLE, with
|
||||
* two sub-states for power management system.
|
||||
* Sub-state 0 - "Deep Sleep" mode with “Instant” wake-up if residency time
|
||||
* is greater or equal to 1 ms
|
||||
* Sub-state 1 - "Deep Sleep" mode with "Standard" wake-up if residency time
|
||||
* is greater or equal to 201 ms
|
||||
*
|
||||
* INCLUDE FILES: soc_clock.h
|
||||
*/
|
||||
|
||||
#include <cmsis_core.h>
|
||||
#include <zephyr/kernel.h>
|
||||
#include <zephyr/drivers/gpio.h>
|
||||
#include <zephyr/drivers/espi.h>
|
||||
#include <zephyr/pm/pm.h>
|
||||
#include <soc.h>
|
||||
|
||||
#include "soc_gpio.h"
|
||||
#include "soc_host.h"
|
||||
#include "soc_power.h"
|
||||
|
||||
#include <zephyr/logging/log.h>
|
||||
LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
|
||||
|
||||
/* The steps that npcx ec enters sleep/deep mode and leaves it. */
|
||||
#define NPCX_ENTER_SYSTEM_SLEEP() ({ \
|
||||
__asm__ volatile ( \
|
||||
"push {r0-r5}\n" /* Save the registers used for delay */ \
|
||||
"wfi\n" /* Enter sleep mode after receiving wfi */ \
|
||||
"ldm %0, {r0-r5}\n" /* Add a delay before instructions fetching */ \
|
||||
"pop {r0-r5}\n" /* Restore the registers used for delay */ \
|
||||
"isb\n" /* Flush the cpu pipelines */ \
|
||||
:: "r" (CONFIG_SRAM_BASE_ADDRESS)); /* A valid addr used for delay */ \
|
||||
})
|
||||
|
||||
/* Variables for tracing */
|
||||
static uint32_t cnt_sleep0;
|
||||
static uint32_t cnt_sleep1;
|
||||
|
||||
/* Supported sleep mode in npcx series */
|
||||
enum {
|
||||
NPCX_SLEEP,
|
||||
NPCX_DEEP_SLEEP,
|
||||
};
|
||||
|
||||
/* Supported wake-up mode in npcx series */
|
||||
enum {
|
||||
NPCX_INSTANT_WAKE_UP,
|
||||
NPCX_STANDARD_WAKE_UP,
|
||||
};
|
||||
|
||||
#define NODE_LEAKAGE_IO DT_INST(0, nuvoton_npcx_leakage_io)
|
||||
#if DT_NODE_HAS_PROP(NODE_LEAKAGE_IO, leak_gpios)
|
||||
struct npcx_leak_gpio {
|
||||
const struct device *gpio;
|
||||
gpio_pin_t pin;
|
||||
};
|
||||
|
||||
#define NPCX_POWER_LEAKAGE_IO_INIT(node_id, prop, idx) { \
|
||||
.gpio = DEVICE_DT_GET(DT_GPIO_CTLR_BY_IDX(node_id, prop, idx)), \
|
||||
.pin = DT_GPIO_PIN_BY_IDX(node_id, prop, idx), \
|
||||
},
|
||||
|
||||
/*
|
||||
* Get io array which have leakage current from 'leak-gpios' property of
|
||||
* 'power_leakage_io' DT node. User can overwrite this prop. at board DT file to
|
||||
* save power consumption when ec enter deep sleep.
|
||||
*
|
||||
* &power_leakage_io {
|
||||
* leak-gpios = <&gpio0 0 0
|
||||
* &gpiob 1 0>;
|
||||
* };
|
||||
*/
|
||||
static struct npcx_leak_gpio leak_gpios[] = {
|
||||
DT_FOREACH_PROP_ELEM(NODE_LEAKAGE_IO, leak_gpios, NPCX_POWER_LEAKAGE_IO_INIT)
|
||||
};
|
||||
|
||||
static void npcx_power_suspend_leak_io_pads(void)
|
||||
{
|
||||
for (int i = 0; i < ARRAY_SIZE(leak_gpios); i++) {
|
||||
npcx_gpio_disable_io_pads(leak_gpios[i].gpio, leak_gpios[i].pin);
|
||||
}
|
||||
}
|
||||
|
||||
static void npcx_power_restore_leak_io_pads(void)
|
||||
{
|
||||
for (int i = 0; i < ARRAY_SIZE(leak_gpios); i++) {
|
||||
npcx_gpio_enable_io_pads(leak_gpios[i].gpio, leak_gpios[i].pin);
|
||||
}
|
||||
}
|
||||
#else
|
||||
void npcx_power_suspend_leak_io_pads(void)
|
||||
{
|
||||
/* do nothing */
|
||||
}
|
||||
|
||||
void npcx_power_restore_leak_io_pads(void)
|
||||
{
|
||||
/* do nothing */
|
||||
}
|
||||
#endif /* DT_NODE_HAS_PROP(NODE_LEAKAGE_IO, leak_gpios) */
|
||||
|
||||
static void npcx_power_enter_system_sleep(int slp_mode, int wk_mode)
|
||||
{
|
||||
/* Disable interrupts */
|
||||
__disable_irq();
|
||||
|
||||
/*
|
||||
* Disable priority mask temporarily to make sure that wake-up events
|
||||
* are visible to the WFI instruction.
|
||||
*/
|
||||
__set_BASEPRI(0);
|
||||
|
||||
/* Configure sleep/deep sleep settings in clock control module. */
|
||||
npcx_clock_control_turn_on_system_sleep(slp_mode == NPCX_DEEP_SLEEP,
|
||||
wk_mode == NPCX_INSTANT_WAKE_UP);
|
||||
|
||||
/*
|
||||
* Disable the connection between io pads that have leakage current and
|
||||
* input buffer to save power consumption.
|
||||
*/
|
||||
npcx_power_suspend_leak_io_pads();
|
||||
|
||||
/* Turn on eSPI/LPC host access wake-up interrupt. */
|
||||
if (IS_ENABLED(CONFIG_ESPI_NPCX)) {
|
||||
npcx_host_enable_access_interrupt();
|
||||
}
|
||||
|
||||
/* Turn on UART RX wake-up interrupt. */
|
||||
if (IS_ENABLED(CONFIG_UART_NPCX)) {
|
||||
npcx_uart_enable_access_interrupt();
|
||||
}
|
||||
|
||||
/*
|
||||
* Capture the reading of low-freq timer for compensation before ec
|
||||
* enters system sleep mode.
|
||||
*/
|
||||
npcx_clock_capture_low_freq_timer();
|
||||
|
||||
/* Enter system sleep mode */
|
||||
NPCX_ENTER_SYSTEM_SLEEP();
|
||||
|
||||
/*
|
||||
* Compensate system timer by the elapsed time of low-freq timer during
|
||||
* system sleep mode.
|
||||
*/
|
||||
npcx_clock_compensate_system_timer();
|
||||
|
||||
/* Turn off eSPI/LPC host access wake-up interrupt. */
|
||||
if (IS_ENABLED(CONFIG_ESPI_NPCX)) {
|
||||
npcx_host_disable_access_interrupt();
|
||||
}
|
||||
|
||||
/*
|
||||
* Restore the connection between io pads that have leakage current and
|
||||
* input buffer.
|
||||
*/
|
||||
npcx_power_restore_leak_io_pads();
|
||||
|
||||
/* Turn off system sleep mode. */
|
||||
npcx_clock_control_turn_off_system_sleep();
|
||||
}
|
||||
|
||||
/* Invoke when enter "Suspend/Low Power" mode. */
|
||||
void pm_state_set(enum pm_state state, uint8_t substate_id)
|
||||
{
|
||||
if (state != PM_STATE_SUSPEND_TO_IDLE) {
|
||||
LOG_DBG("Unsupported power state %u", state);
|
||||
} else {
|
||||
switch (substate_id) {
|
||||
case 0: /* Sub-state 0: Deep sleep with instant wake-up */
|
||||
npcx_power_enter_system_sleep(NPCX_DEEP_SLEEP,
|
||||
NPCX_INSTANT_WAKE_UP);
|
||||
if (IS_ENABLED(CONFIG_NPCX_PM_TRACE)) {
|
||||
cnt_sleep0++;
|
||||
}
|
||||
break;
|
||||
case 1: /* Sub-state 1: Deep sleep with standard wake-up */
|
||||
npcx_power_enter_system_sleep(NPCX_DEEP_SLEEP,
|
||||
NPCX_STANDARD_WAKE_UP);
|
||||
if (IS_ENABLED(CONFIG_NPCX_PM_TRACE)) {
|
||||
cnt_sleep1++;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
LOG_DBG("Unsupported power substate-id %u",
|
||||
substate_id);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Handle soc specific activity after exiting "Suspend/Low Power" mode. */
|
||||
void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
|
||||
{
|
||||
if (state != PM_STATE_SUSPEND_TO_IDLE) {
|
||||
LOG_DBG("Unsupported power state %u", state);
|
||||
} else {
|
||||
switch (substate_id) {
|
||||
case 0: /* Sub-state 0: Deep sleep with instant wake-up */
|
||||
/* Restore interrupts */
|
||||
__enable_irq();
|
||||
break;
|
||||
case 1: /* Sub-state 1: Deep sleep with standard wake-up */
|
||||
/* Restore interrupts */
|
||||
__enable_irq();
|
||||
break;
|
||||
default:
|
||||
LOG_DBG("Unsupported power substate-id %u",
|
||||
substate_id);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (IS_ENABLED(CONFIG_NPCX_PM_TRACE)) {
|
||||
LOG_DBG("sleep: %d, deep sleep: %d", cnt_sleep0, cnt_sleep1);
|
||||
LOG_INF("total ticks in sleep: %lld",
|
||||
npcx_clock_get_sleep_ticks());
|
||||
}
|
||||
}
|
||||
38
soc/nuvoton/npcx/common/reg/reg_access.h
Normal file
38
soc/nuvoton/npcx/common/reg/reg_access.h
Normal file
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _NUVOTON_NPCX_REG_ACCESS_H
|
||||
#define _NUVOTON_NPCX_REG_ACCESS_H
|
||||
|
||||
/*
|
||||
* NPCX register bit/field access operations
|
||||
*/
|
||||
#define IS_BIT_SET(reg, bit) (((reg >> bit) & (0x1)) != 0)
|
||||
|
||||
#define GET_POS_FIELD(pos, size) pos
|
||||
#define GET_SIZE_FIELD(pos, size) size
|
||||
#define FIELD_POS(field) GET_POS_##field
|
||||
#define FIELD_SIZE(field) GET_SIZE_##field
|
||||
|
||||
#define GET_FIELD(reg, field) \
|
||||
_GET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field))
|
||||
#define _GET_FIELD_(reg, f_pos, f_size) (((reg)>>(f_pos)) & ((1<<(f_size))-1))
|
||||
|
||||
#define SET_FIELD(reg, field, value) \
|
||||
_SET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field), value)
|
||||
#define _SET_FIELD_(reg, f_pos, f_size, value) \
|
||||
((reg) = ((reg) & (~(((1 << (f_size))-1) << (f_pos)))) \
|
||||
| ((value) << (f_pos)))
|
||||
|
||||
#define GET_FIELD_POS(field) \
|
||||
_GET_FIELD_POS_(FIELD_POS(field))
|
||||
#define _GET_FIELD_POS_(f_ops) f_ops
|
||||
|
||||
#define GET_FIELD_SZ(field) \
|
||||
_GET_FIELD_SZ_(FIELD_SIZE(field))
|
||||
#define _GET_FIELD_SZ_(f_ops) f_ops
|
||||
|
||||
#endif /* _NUVOTON_NPCX_REG_ACCESS_H */
|
||||
1749
soc/nuvoton/npcx/common/reg/reg_def.h
Normal file
1749
soc/nuvoton/npcx/common/reg/reg_def.h
Normal file
File diff suppressed because it is too large
Load diff
191
soc/nuvoton/npcx/common/registers.c
Normal file
191
soc/nuvoton/npcx/common/registers.c
Normal file
|
|
@ -0,0 +1,191 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/device.h>
|
||||
#include <soc.h>
|
||||
|
||||
/* CDCG register structure check */
|
||||
NPCX_REG_SIZE_CHECK(cdcg_reg, 0x116);
|
||||
NPCX_REG_OFFSET_CHECK(cdcg_reg, HFCBCD, 0x010);
|
||||
NPCX_REG_OFFSET_CHECK(cdcg_reg, HFCBCD2, 0x014);
|
||||
NPCX_REG_OFFSET_CHECK(cdcg_reg, LFCGCTL, 0x100);
|
||||
NPCX_REG_OFFSET_CHECK(cdcg_reg, LFCGCTL2, 0x114);
|
||||
|
||||
/* PMC register structure check */
|
||||
NPCX_REG_SIZE_CHECK(pmc_reg, 0x025);
|
||||
NPCX_REG_OFFSET_CHECK(pmc_reg, ENIDL_CTL, 0x003);
|
||||
NPCX_REG_OFFSET_CHECK(pmc_reg, PWDWN_CTL1, 0x008);
|
||||
NPCX_REG_OFFSET_CHECK(pmc_reg, PWDWN_CTL7, 0x024);
|
||||
|
||||
/* SCFG register structure check */
|
||||
NPCX_REG_SIZE_CHECK(scfg_reg, 0x02f);
|
||||
NPCX_REG_OFFSET_CHECK(scfg_reg, DEV_CTL4, 0x006);
|
||||
NPCX_REG_OFFSET_CHECK(scfg_reg, DEVALT0, 0x010);
|
||||
NPCX_REG_OFFSET_CHECK(scfg_reg, LV_GPIO_CTL0, 0x02a);
|
||||
|
||||
/* GLUE register structure check */
|
||||
NPCX_REG_SIZE_CHECK(glue_reg, 0x028);
|
||||
NPCX_REG_OFFSET_CHECK(glue_reg, SMB_EEN, 0x003);
|
||||
NPCX_REG_OFFSET_CHECK(glue_reg, SDPD0, 0x010);
|
||||
NPCX_REG_OFFSET_CHECK(glue_reg, SMB_SEL, 0x021);
|
||||
NPCX_REG_OFFSET_CHECK(glue_reg, PSL_CTS, 0x027);
|
||||
|
||||
/* UART register structure check */
|
||||
NPCX_REG_SIZE_CHECK(uart_reg, 0x027);
|
||||
NPCX_REG_OFFSET_CHECK(uart_reg, UPSR, 0x00e);
|
||||
NPCX_REG_OFFSET_CHECK(uart_reg, UFTSTS, 0x020);
|
||||
NPCX_REG_OFFSET_CHECK(uart_reg, UFRCTL, 0x026);
|
||||
|
||||
/* GPIO register structure check */
|
||||
NPCX_REG_SIZE_CHECK(gpio_reg, 0x008);
|
||||
NPCX_REG_OFFSET_CHECK(gpio_reg, PLOCK_CTL, 0x007);
|
||||
|
||||
/* PWM register structure check */
|
||||
NPCX_REG_SIZE_CHECK(pwm_reg, 0x00e);
|
||||
NPCX_REG_OFFSET_CHECK(pwm_reg, PWMCTL, 0x004);
|
||||
NPCX_REG_OFFSET_CHECK(pwm_reg, DCR, 0x006);
|
||||
NPCX_REG_OFFSET_CHECK(pwm_reg, PWMCTLEX, 0x00c);
|
||||
|
||||
/* ADC register structure check */
|
||||
NPCX_REG_SIZE_CHECK(adc_reg, 0x028);
|
||||
NPCX_REG_OFFSET_CHECK(adc_reg, THRCTS, 0x01a);
|
||||
NPCX_REG_OFFSET_CHECK(adc_reg, ADCCNF2, 0x020);
|
||||
NPCX_REG_OFFSET_CHECK(adc_reg, MEAST, 0x026);
|
||||
|
||||
/* TWD register structure check */
|
||||
NPCX_REG_SIZE_CHECK(twd_reg, 0x012);
|
||||
NPCX_REG_OFFSET_CHECK(twd_reg, T0CSR, 0x006);
|
||||
NPCX_REG_OFFSET_CHECK(twd_reg, TWMWD, 0x00e);
|
||||
NPCX_REG_OFFSET_CHECK(twd_reg, WDCP, 0x010);
|
||||
|
||||
/* ESPI register structure check */
|
||||
NPCX_REG_SIZE_CHECK(espi_reg, 0x900);
|
||||
NPCX_REG_OFFSET_CHECK(espi_reg, FLASHCFG, 0x034);
|
||||
NPCX_REG_OFFSET_CHECK(espi_reg, NPCX_ONLY_ESPI_REG1, 0x0f0);
|
||||
NPCX_REG_OFFSET_CHECK(espi_reg, VWEVMS, 0x140);
|
||||
NPCX_REG_OFFSET_CHECK(espi_reg, VWGPSM, 0x180);
|
||||
NPCX_REG_OFFSET_CHECK(espi_reg, VWCTL, 0x2fc);
|
||||
NPCX_REG_OFFSET_CHECK(espi_reg, OOBTXBUF, 0x380);
|
||||
NPCX_REG_OFFSET_CHECK(espi_reg, OOBCTL_DIRECT, 0x3fc);
|
||||
NPCX_REG_OFFSET_CHECK(espi_reg, FLASHTXBUF, 0x480);
|
||||
NPCX_REG_OFFSET_CHECK(espi_reg, FLASHCTL_DIRECT, 0x4fc);
|
||||
|
||||
/* MSWC register structure check */
|
||||
NPCX_REG_SIZE_CHECK(mswc_reg, 0x030);
|
||||
NPCX_REG_OFFSET_CHECK(mswc_reg, HCBAL, 0x008);
|
||||
NPCX_REG_OFFSET_CHECK(mswc_reg, HCBAH, 0x00a);
|
||||
NPCX_REG_OFFSET_CHECK(mswc_reg, SRID_CR, 0x01c);
|
||||
NPCX_REG_OFFSET_CHECK(mswc_reg, SID_CR, 0x020);
|
||||
NPCX_REG_OFFSET_CHECK(mswc_reg, VW_SLPST1, 0x02e);
|
||||
|
||||
/* SHM register structure check */
|
||||
NPCX_REG_SIZE_CHECK(shm_reg, 0x050);
|
||||
NPCX_REG_OFFSET_CHECK(shm_reg, IMA_WIN_SIZE, 0x005);
|
||||
NPCX_REG_OFFSET_CHECK(shm_reg, WIN_SIZE, 0x007);
|
||||
NPCX_REG_OFFSET_CHECK(shm_reg, IMA_SEM, 0x00b);
|
||||
NPCX_REG_OFFSET_CHECK(shm_reg, SHCFG, 0x00e);
|
||||
NPCX_REG_OFFSET_CHECK(shm_reg, WIN1_WR_PROT, 0x010);
|
||||
NPCX_REG_OFFSET_CHECK(shm_reg, IMA_WR_PROT, 0x016);
|
||||
NPCX_REG_OFFSET_CHECK(shm_reg, WIN_BASE1, 0x020);
|
||||
NPCX_REG_OFFSET_CHECK(shm_reg, WIN_BASE2, 0x024);
|
||||
NPCX_REG_OFFSET_CHECK(shm_reg, RST_CFG, 0x03a);
|
||||
NPCX_REG_OFFSET_CHECK(shm_reg, DP80BUF, 0x040);
|
||||
NPCX_REG_OFFSET_CHECK(shm_reg, DP80CTL, 0x044);
|
||||
NPCX_REG_OFFSET_CHECK(shm_reg, HOFS_STS, 0x048);
|
||||
NPCX_REG_OFFSET_CHECK(shm_reg, COFS1, 0x04c);
|
||||
|
||||
/* KBC register structure check */
|
||||
NPCX_REG_SIZE_CHECK(kbc_reg, 0x00c);
|
||||
NPCX_REG_OFFSET_CHECK(kbc_reg, HIKMDI, 0x00a);
|
||||
NPCX_REG_OFFSET_CHECK(kbc_reg, SHIKMDI, 0x00b);
|
||||
|
||||
/* PMCH register structure check */
|
||||
NPCX_REG_SIZE_CHECK(pmch_reg, 0x012);
|
||||
NPCX_REG_OFFSET_CHECK(pmch_reg, HIPMDO, 0x002);
|
||||
NPCX_REG_OFFSET_CHECK(pmch_reg, HIPMDOC, 0x006);
|
||||
NPCX_REG_OFFSET_CHECK(pmch_reg, HIPMDOM, 0x008);
|
||||
NPCX_REG_OFFSET_CHECK(pmch_reg, HIPMDIC, 0x00a);
|
||||
NPCX_REG_OFFSET_CHECK(pmch_reg, HIPMIE, 0x010);
|
||||
|
||||
/* C2H register structure check */
|
||||
NPCX_REG_SIZE_CHECK(c2h_reg, 0x00c);
|
||||
NPCX_REG_OFFSET_CHECK(c2h_reg, LKSIOHA, 0x004);
|
||||
NPCX_REG_OFFSET_CHECK(c2h_reg, CRSMAE, 0x008);
|
||||
NPCX_REG_OFFSET_CHECK(c2h_reg, SIBCTRL, 0x00a);
|
||||
|
||||
/* SMB register structure check */
|
||||
NPCX_REG_SIZE_CHECK(smb_reg, 0x020);
|
||||
NPCX_REG_OFFSET_CHECK(smb_reg, SMBCTL1, 0x006);
|
||||
NPCX_REG_OFFSET_CHECK(smb_reg, SMBT_OUT, 0x00f);
|
||||
NPCX_REG_OFFSET_CHECK(smb_reg, SMBADDR6, 0x016);
|
||||
NPCX_REG_OFFSET_CHECK(smb_reg, SMBCST2, 0x018);
|
||||
NPCX_REG_OFFSET_CHECK(smb_reg, SMBTXF_STS, 0x01a);
|
||||
NPCX_REG_OFFSET_CHECK(smb_reg, SMBSCLHT, 0x01e);
|
||||
NPCX_REG_OFFSET_CHECK(smb_reg, SMBRXF_CTL, 0x01e);
|
||||
|
||||
/* ITIM register structure check */
|
||||
NPCX_REG_SIZE_CHECK(itim32_reg, 0x00c);
|
||||
NPCX_REG_OFFSET_CHECK(itim32_reg, ITPRE32, 0x001);
|
||||
NPCX_REG_OFFSET_CHECK(itim32_reg, ITCTS32, 0x004);
|
||||
NPCX_REG_OFFSET_CHECK(itim32_reg, ITCNT32, 0x008);
|
||||
|
||||
NPCX_REG_SIZE_CHECK(itim64_reg, 0x010);
|
||||
NPCX_REG_OFFSET_CHECK(itim64_reg, ITPRE64, 0x001);
|
||||
NPCX_REG_OFFSET_CHECK(itim64_reg, ITCTS64, 0x004);
|
||||
NPCX_REG_OFFSET_CHECK(itim64_reg, ITCNT64L, 0x008);
|
||||
NPCX_REG_OFFSET_CHECK(itim64_reg, ITCNT64H, 0x00c);
|
||||
|
||||
/* TACH register structure check */
|
||||
NPCX_REG_SIZE_CHECK(tach_reg, 0x01e);
|
||||
NPCX_REG_OFFSET_CHECK(tach_reg, TPRSC, 0x008);
|
||||
NPCX_REG_OFFSET_CHECK(tach_reg, TECLR, 0x010);
|
||||
NPCX_REG_OFFSET_CHECK(tach_reg, TCPA, 0x014);
|
||||
NPCX_REG_OFFSET_CHECK(tach_reg, TCPCFG, 0x018);
|
||||
NPCX_REG_OFFSET_CHECK(tach_reg, TCFG, 0x01c);
|
||||
|
||||
/* Debug Interface register structure check */
|
||||
NPCX_REG_SIZE_CHECK(dbg_reg, 0x06);
|
||||
NPCX_REG_OFFSET_CHECK(dbg_reg, DBGCTRL, 0x000);
|
||||
NPCX_REG_OFFSET_CHECK(dbg_reg, DBGFRZEN2, 0x003);
|
||||
NPCX_REG_OFFSET_CHECK(dbg_reg, DBGFRZEN4, 0x005);
|
||||
|
||||
/* PS/2 Interface register structure check */
|
||||
NPCX_REG_SIZE_CHECK(ps2_reg, 0x00c);
|
||||
NPCX_REG_OFFSET_CHECK(ps2_reg, PSDAT, 0x000);
|
||||
NPCX_REG_OFFSET_CHECK(ps2_reg, PSTAT, 0x002);
|
||||
NPCX_REG_OFFSET_CHECK(ps2_reg, PSCON, 0x004);
|
||||
NPCX_REG_OFFSET_CHECK(ps2_reg, PSOSIG, 0x006);
|
||||
NPCX_REG_OFFSET_CHECK(ps2_reg, PSISIG, 0x008);
|
||||
NPCX_REG_OFFSET_CHECK(ps2_reg, PSIEN, 0x00a);
|
||||
|
||||
/* FIU register structure check */
|
||||
#if defined(CONFIG_SOC_SERIES_NPCX9) || defined(CONFIG_SOC_SERIES_NPCX4)
|
||||
NPCX_REG_SIZE_CHECK(fiu_reg, 0x040);
|
||||
#else
|
||||
NPCX_REG_SIZE_CHECK(fiu_reg, 0x034);
|
||||
#endif
|
||||
NPCX_REG_OFFSET_CHECK(fiu_reg, BURST_CFG, 0x001);
|
||||
NPCX_REG_OFFSET_CHECK(fiu_reg, SPI_FL_CFG, 0x014);
|
||||
NPCX_REG_OFFSET_CHECK(fiu_reg, UMA_CTS, 0x01e);
|
||||
NPCX_REG_OFFSET_CHECK(fiu_reg, CRCCON, 0x026);
|
||||
NPCX_REG_OFFSET_CHECK(fiu_reg, FIU_RD_CMD, 0x030);
|
||||
NPCX_REG_OFFSET_CHECK(fiu_reg, FIU_EXT_CFG, 0x033);
|
||||
|
||||
/* PECI register structure check */
|
||||
NPCX_REG_SIZE_CHECK(peci_reg, 0x050);
|
||||
NPCX_REG_OFFSET_CHECK(peci_reg, PECI_ADDR, 0x002);
|
||||
NPCX_REG_OFFSET_CHECK(peci_reg, PECI_WR_LENGTH, 0x007);
|
||||
NPCX_REG_OFFSET_CHECK(peci_reg, PECI_WR_FCS, 0x00b);
|
||||
|
||||
/* KBS register structure check */
|
||||
NPCX_REG_SIZE_CHECK(kbs_reg, 0x010);
|
||||
NPCX_REG_OFFSET_CHECK(kbs_reg, KBSIN, 0x004);
|
||||
NPCX_REG_OFFSET_CHECK(kbs_reg, KBSOUT0, 0x006);
|
||||
NPCX_REG_OFFSET_CHECK(kbs_reg, KBS_BUF_INDX, 0x00a);
|
||||
|
||||
/* SPIP register structure check */
|
||||
NPCX_REG_SIZE_CHECK(spip_reg, 0x006);
|
||||
NPCX_REG_OFFSET_CHECK(spip_reg, SPIP_CTL1, 0x002);
|
||||
156
soc/nuvoton/npcx/common/scfg.c
Normal file
156
soc/nuvoton/npcx/common/scfg.c
Normal file
|
|
@ -0,0 +1,156 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/init.h>
|
||||
#include <zephyr/drivers/gpio.h>
|
||||
#include <zephyr/dt-bindings/pinctrl/npcx-pinctrl.h>
|
||||
#include <zephyr/kernel.h>
|
||||
#include <soc.h>
|
||||
|
||||
#include "soc_gpio.h"
|
||||
|
||||
#include <zephyr/logging/log.h>
|
||||
LOG_MODULE_REGISTER(pimux_npcx, LOG_LEVEL_ERR);
|
||||
|
||||
/* Driver config */
|
||||
struct npcx_scfg_config {
|
||||
/* scfg device base address */
|
||||
uintptr_t base_scfg;
|
||||
uintptr_t base_dbg;
|
||||
uintptr_t base_glue;
|
||||
};
|
||||
|
||||
/*
|
||||
* Get io list which default functionality are not IOs. Then switch them to
|
||||
* GPIO in pin-mux init function.
|
||||
*
|
||||
* def-io-conf-list {
|
||||
* pinmux = <&alt0_gpio_no_spip
|
||||
* &alt0_gpio_no_fpip
|
||||
* ...>;
|
||||
* };
|
||||
*/
|
||||
#define NPCX_NO_GPIO_ALT_ITEM(node_id, prop, idx) { \
|
||||
.group = DT_PHA(DT_PROP_BY_IDX(node_id, prop, idx), alts, group), \
|
||||
.bit = DT_PHA(DT_PROP_BY_IDX(node_id, prop, idx), alts, bit), \
|
||||
.inverted = DT_PHA(DT_PROP_BY_IDX(node_id, prop, idx), alts, inv), \
|
||||
},
|
||||
|
||||
static const struct npcx_alt def_alts[] = {
|
||||
DT_FOREACH_PROP_ELEM(DT_INST(0, nuvoton_npcx_pinctrl_def), pinmux,
|
||||
NPCX_NO_GPIO_ALT_ITEM)
|
||||
};
|
||||
|
||||
static const struct npcx_scfg_config npcx_scfg_cfg = {
|
||||
.base_scfg = DT_REG_ADDR_BY_NAME(DT_NODELABEL(scfg), scfg),
|
||||
.base_dbg = DT_REG_ADDR_BY_NAME(DT_NODELABEL(scfg), dbg),
|
||||
.base_glue = DT_REG_ADDR_BY_NAME(DT_NODELABEL(scfg), glue),
|
||||
};
|
||||
|
||||
/* Driver convenience defines */
|
||||
#define HAL_SFCG_INST() (struct scfg_reg *)(npcx_scfg_cfg.base_scfg)
|
||||
|
||||
#define HAL_GLUE_INST() (struct glue_reg *)(npcx_scfg_cfg.base_glue)
|
||||
|
||||
/* Pin-control local functions */
|
||||
static void npcx_pinctrl_alt_sel(const struct npcx_alt *alt, int alt_func)
|
||||
{
|
||||
const uint32_t scfg_base = npcx_scfg_cfg.base_scfg;
|
||||
uint8_t alt_mask = BIT(alt->bit);
|
||||
|
||||
/*
|
||||
* alt_fun == 0 means select GPIO, otherwise Alternate Func.
|
||||
* inverted == 0:
|
||||
* Set devalt bit to select Alternate Func.
|
||||
* inverted == 1:
|
||||
* Clear devalt bit to select Alternate Func.
|
||||
*/
|
||||
if (!!alt_func != !!alt->inverted) {
|
||||
NPCX_DEVALT(scfg_base, alt->group) |= alt_mask;
|
||||
} else {
|
||||
NPCX_DEVALT(scfg_base, alt->group) &= ~alt_mask;
|
||||
}
|
||||
}
|
||||
|
||||
/* Platform specific pin-control functions */
|
||||
void npcx_lvol_set_detect_level(int lvol_ctrl, int lvol_bit, bool enable)
|
||||
{
|
||||
const uintptr_t scfg_base = npcx_scfg_cfg.base_scfg;
|
||||
|
||||
if (enable) {
|
||||
NPCX_LV_GPIO_CTL(scfg_base, lvol_ctrl) |= BIT(lvol_bit);
|
||||
} else {
|
||||
NPCX_LV_GPIO_CTL(scfg_base, lvol_ctrl) &= ~BIT(lvol_bit);
|
||||
}
|
||||
}
|
||||
|
||||
bool npcx_lvol_get_detect_level(int lvol_ctrl, int lvol_bit)
|
||||
{
|
||||
const uintptr_t scfg_base = npcx_scfg_cfg.base_scfg;
|
||||
|
||||
return NPCX_LV_GPIO_CTL(scfg_base, lvol_ctrl) & BIT(lvol_bit);
|
||||
}
|
||||
|
||||
void npcx_pinctrl_i2c_port_sel(int controller, int port)
|
||||
{
|
||||
struct glue_reg *const inst_glue = HAL_GLUE_INST();
|
||||
|
||||
if (port != 0) {
|
||||
inst_glue->SMB_SEL |= BIT(controller);
|
||||
} else {
|
||||
inst_glue->SMB_SEL &= ~BIT(controller);
|
||||
}
|
||||
}
|
||||
|
||||
int npcx_pinctrl_flash_write_protect_set(void)
|
||||
{
|
||||
struct scfg_reg *inst_scfg = HAL_SFCG_INST();
|
||||
|
||||
inst_scfg->DEV_CTL4 |= BIT(NPCX_DEV_CTL4_WP_IF);
|
||||
if (!IS_BIT_SET(inst_scfg->DEV_CTL4, NPCX_DEV_CTL4_WP_IF)) {
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool npcx_pinctrl_flash_write_protect_is_set(void)
|
||||
{
|
||||
struct scfg_reg *inst_scfg = HAL_SFCG_INST();
|
||||
|
||||
return IS_BIT_SET(inst_scfg->DEV_CTL4, NPCX_DEV_CTL4_WP_IF);
|
||||
}
|
||||
|
||||
void npcx_host_interface_sel(enum npcx_hif_type hif_type)
|
||||
{
|
||||
struct scfg_reg *inst_scfg = HAL_SFCG_INST();
|
||||
|
||||
SET_FIELD(inst_scfg->DEVCNT, NPCX_DEVCNT_HIF_TYP_SEL_FIELD, hif_type);
|
||||
}
|
||||
|
||||
void npcx_dbg_freeze_enable(bool enable)
|
||||
{
|
||||
const uintptr_t dbg_base = npcx_scfg_cfg.base_dbg;
|
||||
|
||||
if (enable) {
|
||||
NPCX_DBGFRZEN3(dbg_base) &= ~BIT(NPCX_DBGFRZEN3_GLBL_FRZ_DIS);
|
||||
} else {
|
||||
NPCX_DBGFRZEN3(dbg_base) |= BIT(NPCX_DBGFRZEN3_GLBL_FRZ_DIS);
|
||||
}
|
||||
}
|
||||
|
||||
/* Pin-control driver registration */
|
||||
static int npcx_scfg_init(void)
|
||||
{
|
||||
/* Change all pads whose default functionality isn't IO to GPIO */
|
||||
for (int i = 0; i < ARRAY_SIZE(def_alts); i++) {
|
||||
npcx_pinctrl_alt_sel(&def_alts[i], 0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(npcx_scfg_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
|
||||
202
soc/nuvoton/npcx/common/soc_clock.h
Normal file
202
soc/nuvoton/npcx/common/soc_clock.h
Normal file
|
|
@ -0,0 +1,202 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _NUVOTON_NPCX_SOC_CLOCK_H_
|
||||
#define _NUVOTON_NPCX_SOC_CLOCK_H_
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Common clock control device node for all NPCX series */
|
||||
#define NPCX_CLK_CTRL_NODE DT_NODELABEL(pcc)
|
||||
|
||||
/**
|
||||
* @brief NPCX clock configuration structure
|
||||
*
|
||||
* Used to indicate the device's clock bus type and corresponding PWDWN_CTL
|
||||
* register/bit to turn on/off its source clock.
|
||||
*/
|
||||
struct npcx_clk_cfg {
|
||||
uint16_t bus:8;
|
||||
uint16_t ctrl:5;
|
||||
uint16_t bit:3;
|
||||
};
|
||||
|
||||
/* Clock settings from pcc node */
|
||||
/* Target OFMCLK freq */
|
||||
#define OFMCLK DT_PROP(DT_NODELABEL(pcc), clock_frequency)
|
||||
/* Core clock prescaler */
|
||||
#define FPRED_VAL (DT_PROP(DT_NODELABEL(pcc), core_prescaler) - 1)
|
||||
/* APB1 clock divider */
|
||||
#define APB1DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb1_prescaler) - 1)
|
||||
/* APB2 clock divider */
|
||||
#define APB2DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb2_prescaler) - 1)
|
||||
/* APB3 clock divider */
|
||||
#define APB3DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb3_prescaler) - 1)
|
||||
/* APB4 clock divider if supported */
|
||||
#if DT_NODE_HAS_PROP(DT_NODELABEL(pcc), apb4_prescaler)
|
||||
#if defined(CONFIG_CLOCK_CONTROL_NPCX_SUPP_APB4) /* Supported in NPCX9 and later series */
|
||||
#define APB4DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb4_prescaler) - 1)
|
||||
#else
|
||||
#error "APB4 clock divider is not supported but defined in pcc node!"
|
||||
#endif /* CONFIG_CLOCK_CONTROL_NPCX_SUPP_APB4 */
|
||||
#endif
|
||||
|
||||
/* Construct a uint8_t array from 'pwdwn-ctl-val' prop for PWDWN_CTL initialization. */
|
||||
#define NPCX_PWDWN_CTL_ITEMS_INIT(node, prop, idx) DT_PROP_BY_IDX(node, prop, idx),
|
||||
#define NPCX_PWDWN_CTL_INIT DT_FOREACH_PROP_ELEM(DT_NODELABEL(pcc), \
|
||||
pwdwn_ctl_val, NPCX_PWDWN_CTL_ITEMS_INIT)
|
||||
|
||||
/*
|
||||
* NPCX7 and later series clock tree macros:
|
||||
* (Please refer Figure 58. for more information.)
|
||||
*
|
||||
* Maximum OFMCLK in npcx7/9 series is 100MHz,
|
||||
* Maximum OFMCLK in npcx4 series is 120MHz,
|
||||
*
|
||||
* Suggestion for npcx series:
|
||||
* - OFMCLK > MAX_OFMCLK/2, XF_RANGE should be 1, else 0.
|
||||
* - CORE_CLK > MAX_OFMCLK/2, AHB6DIV should be 1, else 0.
|
||||
* - CORE_CLK > MAX_OFMCLK/2, FIUDIV should be 1, else 0.
|
||||
*/
|
||||
/* Core domain clock */
|
||||
#define CORE_CLK (OFMCLK / DT_PROP(DT_NODELABEL(pcc), core_prescaler))
|
||||
/* Low Frequency clock */
|
||||
#define LFCLK 32768
|
||||
|
||||
/* FMUL clock */
|
||||
#if (OFMCLK > (MAX_OFMCLK / 2))
|
||||
#define FMCLK (OFMCLK / 2) /* FMUL clock = OFMCLK/2 */
|
||||
#else
|
||||
#define FMCLK OFMCLK /* FMUL clock = OFMCLK */
|
||||
#endif
|
||||
|
||||
/* APBs source clock */
|
||||
#define APBSRC_CLK OFMCLK
|
||||
|
||||
/* AHB6 clock */
|
||||
#if (CORE_CLK > (MAX_OFMCLK / 2))
|
||||
#define AHB6DIV_VAL 1 /* AHB6_CLK = CORE_CLK/2 */
|
||||
#else
|
||||
#define AHB6DIV_VAL 0 /* AHB6_CLK = CORE_CLK */
|
||||
#endif
|
||||
|
||||
/* FIU clock divider */
|
||||
#if (CORE_CLK > (MAX_OFMCLK / 2))
|
||||
#define FIUDIV_VAL 1 /* FIU_CLK = CORE_CLK/2 */
|
||||
#else
|
||||
#define FIUDIV_VAL 0 /* FIU_CLK = CORE_CLK */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CLOCK_CONTROL_NPCX_SUPP_FIU1)
|
||||
#if (CORE_CLK > (MAX_OFMCLK / 2))
|
||||
#define FIU1DIV_VAL 1 /* FIU1_CLK = CORE_CLK/2 */
|
||||
#else
|
||||
#define FIU1DIV_VAL 0 /* FIU1_CLK = CORE_CLK */
|
||||
#endif
|
||||
#endif /* CONFIG_CLOCK_CONTROL_NPCX_SUPP_FIU1 */
|
||||
|
||||
/* Get APB clock freq */
|
||||
#define NPCX_APB_CLOCK(no) (APBSRC_CLK / (APB##no##DIV_VAL + 1))
|
||||
|
||||
/*
|
||||
* Frequency multiplier M/N value definitions according to the requested
|
||||
* OFMCLK (Unit:Hz).
|
||||
*/
|
||||
#if (OFMCLK > (MAX_OFMCLK / 2))
|
||||
#define HFCGN_VAL 0x82 /* Set XF_RANGE as 1 */
|
||||
#else
|
||||
#define HFCGN_VAL 0x02
|
||||
#endif
|
||||
#if (OFMCLK == 120000000)
|
||||
#define HFCGMH_VAL 0x0E
|
||||
#define HFCGML_VAL 0x4E
|
||||
#elif (OFMCLK == 100000000)
|
||||
#define HFCGMH_VAL 0x0B
|
||||
#define HFCGML_VAL 0xEC
|
||||
#elif (OFMCLK == 96000000)
|
||||
#define HFCGMH_VAL 0x0B
|
||||
#define HFCGML_VAL 0x72
|
||||
#elif (OFMCLK == 90000000)
|
||||
#define HFCGMH_VAL 0x0A
|
||||
#define HFCGML_VAL 0xBA
|
||||
#elif (OFMCLK == 80000000)
|
||||
#define HFCGMH_VAL 0x09
|
||||
#define HFCGML_VAL 0x89
|
||||
#elif (OFMCLK == 66000000)
|
||||
#define HFCGMH_VAL 0x07
|
||||
#define HFCGML_VAL 0xDE
|
||||
#elif (OFMCLK == 50000000)
|
||||
#define HFCGMH_VAL 0x0B
|
||||
#define HFCGML_VAL 0xEC
|
||||
#elif (OFMCLK == 48000000)
|
||||
#define HFCGMH_VAL 0x0B
|
||||
#define HFCGML_VAL 0x72
|
||||
#else
|
||||
#error "Unsupported OFMCLK Frequency"
|
||||
#endif
|
||||
|
||||
/* Clock prescaler configurations in different series */
|
||||
#define VAL_HFCGP ((FPRED_VAL << 4) | AHB6DIV_VAL)
|
||||
#if defined(FIU1DIV_VAL)
|
||||
#define VAL_HFCBCD ((FIU1DIV_VAL << 4) | (FIUDIV_VAL << 2))
|
||||
#else
|
||||
#define VAL_HFCBCD (FIUDIV_VAL << 4)
|
||||
#endif /* FIU1DIV_VAL */
|
||||
#define VAL_HFCBCD1 (APB1DIV_VAL | (APB2DIV_VAL << 4))
|
||||
#if defined(APB4DIV_VAL)
|
||||
#define VAL_HFCBCD2 (APB3DIV_VAL | (APB4DIV_VAL << 4))
|
||||
#else
|
||||
#define VAL_HFCBCD2 APB3DIV_VAL
|
||||
#endif /* APB4DIV_VAL */
|
||||
|
||||
/**
|
||||
* @brief Function to notify clock driver that backup the counter value of
|
||||
* low-frequency timer before ec entered deep idle state.
|
||||
*/
|
||||
void npcx_clock_capture_low_freq_timer(void);
|
||||
|
||||
/**
|
||||
* @brief Function to notify clock driver that compensate the counter value of
|
||||
* system timer by low-frequency timer after ec left deep idle state.
|
||||
*
|
||||
*/
|
||||
void npcx_clock_compensate_system_timer(void);
|
||||
|
||||
/**
|
||||
* @brief Function to get time ticks in system sleep/deep sleep state. The unit
|
||||
* is ticks.
|
||||
*
|
||||
*/
|
||||
uint64_t npcx_clock_get_sleep_ticks(void);
|
||||
|
||||
/**
|
||||
* @brief Function to configure system sleep settings. After ec received "wfi"
|
||||
* instruction, ec will enter sleep/deep sleep state for better power
|
||||
* consumption.
|
||||
*
|
||||
* @param is_deep A boolean indicating ec enters deep sleep or sleep state
|
||||
* @param is_instant A boolean indicating 'Instant Wake-up' from deep idle is
|
||||
* enabled
|
||||
*/
|
||||
void npcx_clock_control_turn_on_system_sleep(bool is_deep, bool is_instant);
|
||||
|
||||
/**
|
||||
* @brief Function to turn off system sleep mode.
|
||||
*/
|
||||
void npcx_clock_control_turn_off_system_sleep(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _NUVOTON_NPCX_SOC_CLOCK_H_ */
|
||||
26
soc/nuvoton/npcx/common/soc_dbg.h
Normal file
26
soc/nuvoton/npcx/common/soc_dbg.h
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _NUVOTON_NPCX_SOC_DBG_H_
|
||||
#define _NUVOTON_NPCX_SOC_DBG_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Configure the Automatic Freeze mode. If this mode is enabled, whenever
|
||||
* the Core is halted, various modules’ clocks, counters are stopped and
|
||||
* destructive reads are disabled, pending the respective module enable bit for
|
||||
* debugging.
|
||||
*/
|
||||
void npcx_dbg_freeze_enable(bool enable);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _NUVOTON_NPCX_SOC_DBG_H_ */
|
||||
404
soc/nuvoton/npcx/common/soc_dt.h
Normal file
404
soc/nuvoton/npcx/common/soc_dt.h
Normal file
|
|
@ -0,0 +1,404 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _NUVOTON_NPCX_SOC_DT_H_
|
||||
#define _NUVOTON_NPCX_SOC_DT_H_
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/irq.h>
|
||||
#include <zephyr/sys/util_macro.h>
|
||||
|
||||
/**
|
||||
* @brief Like DT_PROP(), but expand parameters with
|
||||
* DT_ENUM_UPPER_TOKEN not DT_PROP
|
||||
*
|
||||
* If the prop exists, this expands to DT_ENUM_UPPER_TOKEN(node_id, prop).
|
||||
* The default_value parameter is not expanded in this case.
|
||||
*
|
||||
* Otherwise, this expands to default_value.
|
||||
*
|
||||
* @param node_id node identifier
|
||||
* @param prop lowercase-and-underscores property name
|
||||
* @param default_value a fallback value to expand to
|
||||
* @return the property's enum upper token value or default_value
|
||||
*/
|
||||
#define NPCX_DT_PROP_ENUM_OR(node_id, prop, default_value) \
|
||||
COND_CODE_1(DT_NODE_HAS_PROP(node_id, prop), \
|
||||
(DT_STRING_UPPER_TOKEN(node_id, prop)), (default_value))
|
||||
|
||||
/**
|
||||
* @brief Like DT_INST_PROP_OR(), but expand parameters with
|
||||
* NPCX_DT_PROP_ENUM_OR not DT_PROP_OR
|
||||
* @param inst instance number
|
||||
* @param prop lowercase-and-underscores property name
|
||||
* @param default_value a fallback value to expand to
|
||||
* @return the property's enum upper token value or default_value
|
||||
*/
|
||||
#define NPCX_DT_INST_PROP_ENUM_OR(inst, prop, default_value) \
|
||||
NPCX_DT_PROP_ENUM_OR(DT_DRV_INST(inst), prop, default_value)
|
||||
|
||||
/**
|
||||
* @brief Construct a npcx_clk_cfg item from first item in 'clocks' prop which
|
||||
* type is 'phandle-array' to handle "clock-cells" in current driver.
|
||||
*
|
||||
* Example devicetree fragment:
|
||||
* / {
|
||||
* uart1: serial@400c4000 {
|
||||
* clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL1 4>;
|
||||
* ...
|
||||
* };
|
||||
* };
|
||||
*
|
||||
* Example usage:
|
||||
* const struct npcx_clk_cfg clk_cfg = NPCX_DT_CLK_CFG_ITEM(inst);
|
||||
*
|
||||
* @param inst instance number for compatible defined in DT_DRV_COMPAT.
|
||||
* @return npcx_clk_cfg item.
|
||||
*/
|
||||
#define NPCX_DT_CLK_CFG_ITEM(inst) \
|
||||
{ \
|
||||
.bus = NPCX_DT_INST_PROP_ENUM_OR(inst, clock_bus, \
|
||||
DT_PHA(DT_DRV_INST(inst), clocks, bus)), \
|
||||
.ctrl = DT_PHA(DT_DRV_INST(inst), clocks, ctl), \
|
||||
.bit = DT_PHA(DT_DRV_INST(inst), clocks, bit), \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Construct a npcx_clk_cfg structure from 'clocks' property at index 'i'
|
||||
*
|
||||
* @param inst instance number for compatible defined in DT_DRV_COMPAT.
|
||||
* @param i index of clocks prop which type is 'phandle-array'
|
||||
* @return npcx_clk_cfg item from 'clocks' property at index 'i'
|
||||
*/
|
||||
#define NPCX_DT_CLK_CFG_ITEM_BY_IDX(inst, i) \
|
||||
{ \
|
||||
.bus = DT_CLOCKS_CELL_BY_IDX(DT_DRV_INST(inst), i, bus), \
|
||||
.ctrl = DT_CLOCKS_CELL_BY_IDX(DT_DRV_INST(inst), i, ctl), \
|
||||
.bit = DT_CLOCKS_CELL_BY_IDX(DT_DRV_INST(inst), i, bit), \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Length of 'clocks' property which type is 'phandle-array'
|
||||
*
|
||||
* @param inst instance number for compatible defined in DT_DRV_COMPAT.
|
||||
* @return length of 'clocks' property which type is 'phandle-array'
|
||||
*/
|
||||
#define NPCX_DT_CLK_CFG_ITEMS_LEN(inst) DT_INST_PROP_LEN(inst, clocks)
|
||||
|
||||
/**
|
||||
* @brief Macro function to construct npcx_clk_cfg item in UTIL_LISTIFY
|
||||
* extension.
|
||||
*
|
||||
* @param child child index in UTIL_LISTIFY extension.
|
||||
* @param inst instance number for compatible defined in DT_DRV_COMPAT.
|
||||
* @return macro function to construct a npcx_clk_cfg structure.
|
||||
*/
|
||||
#define NPCX_DT_CLK_CFG_ITEMS_FUNC(child, inst) \
|
||||
NPCX_DT_CLK_CFG_ITEM_BY_IDX(inst, child)
|
||||
|
||||
/**
|
||||
* @brief Macro function to construct a list of npcx_clk_cfg items by
|
||||
* UTIL_LISTIFY func
|
||||
*
|
||||
* Example devicetree fragment:
|
||||
* / {
|
||||
* host_sub: lpc@400c1000 {
|
||||
* clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 3>,
|
||||
* <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 4>,
|
||||
* <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 5>,
|
||||
* <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 6>,
|
||||
* <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 7>;
|
||||
* ...
|
||||
* };
|
||||
* Example usage:
|
||||
* const struct npcx_clk_cfg clk_cfg[] = NPCX_DT_CLK_CFG_ITEMS_LIST(0);
|
||||
*
|
||||
* @param inst instance number for compatible defined in DT_DRV_COMPAT.
|
||||
* @return an array of npcx_clk_cfg items.
|
||||
*/
|
||||
#define NPCX_DT_CLK_CFG_ITEMS_LIST(inst) { \
|
||||
LISTIFY(NPCX_DT_CLK_CFG_ITEMS_LEN(inst), \
|
||||
NPCX_DT_CLK_CFG_ITEMS_FUNC, (,), \
|
||||
inst) \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get phandle from "name" property which contains wui information.
|
||||
*
|
||||
* @param inst instance number for compatible defined in DT_DRV_COMPAT.
|
||||
* @param name property 'name' which type is 'phandle' and contains wui info.
|
||||
* @return phandle from 'name' property.
|
||||
*/
|
||||
#define NPCX_DT_PHANDLE_FROM_WUI_NAME(inst, name) \
|
||||
DT_INST_PHANDLE(inst, name)
|
||||
|
||||
/**
|
||||
* @brief Construct a npcx_wui structure from 'name' property
|
||||
*
|
||||
* @param inst instance number for compatible defined in DT_DRV_COMPAT.
|
||||
* @param name property 'name'which type is 'phandle' and contains wui info.
|
||||
* @return npcx_wui item from 'name' property.
|
||||
*/
|
||||
#define NPCX_DT_WUI_ITEM_BY_NAME(inst, name) \
|
||||
{ \
|
||||
.table = DT_PROP(DT_PHANDLE(NPCX_DT_PHANDLE_FROM_WUI_NAME(inst, \
|
||||
name), miwus), index), \
|
||||
.group = DT_PHA(NPCX_DT_PHANDLE_FROM_WUI_NAME(inst, name), miwus, \
|
||||
group), \
|
||||
.bit = DT_PHA(NPCX_DT_PHANDLE_FROM_WUI_NAME(inst, name), miwus, \
|
||||
bit), \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get phandle from 'wui-maps' prop which type is 'phandles' at index 'i'
|
||||
*
|
||||
* @param inst instance number for compatible defined in DT_DRV_COMPAT.
|
||||
* @param i index of 'wui-maps' prop which type is 'phandles'
|
||||
* @return phandle from 'wui-maps' prop at index 'i'
|
||||
*/
|
||||
#define NPCX_DT_PHANDLE_FROM_WUI_MAPS(inst, i) \
|
||||
DT_INST_PHANDLE_BY_IDX(inst, wui_maps, i)
|
||||
|
||||
/**
|
||||
* @brief Construct a npcx_wui structure from wui-maps property at index 'i'
|
||||
*
|
||||
* @param inst instance number for compatible defined in DT_DRV_COMPAT.
|
||||
* @param i index of 'wui-maps' prop which type is 'phandles'
|
||||
* @return npcx_wui item at index 'i'
|
||||
*/
|
||||
#define NPCX_DT_WUI_ITEM_BY_IDX(inst, i) \
|
||||
{ \
|
||||
.table = DT_PROP(DT_PHANDLE(NPCX_DT_PHANDLE_FROM_WUI_MAPS(inst, i), \
|
||||
miwus), index), \
|
||||
.group = DT_PHA(NPCX_DT_PHANDLE_FROM_WUI_MAPS(inst, i), miwus, \
|
||||
group), \
|
||||
.bit = DT_PHA(NPCX_DT_PHANDLE_FROM_WUI_MAPS(inst, i), miwus, bit), \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Length of npcx_wui structures in 'wui-maps' property
|
||||
*
|
||||
* @param inst instance number for compatible defined in DT_DRV_COMPAT.
|
||||
* @return length of 'wui-maps' prop which type is 'phandles'
|
||||
*/
|
||||
#define NPCX_DT_WUI_ITEMS_LEN(inst) DT_INST_PROP_LEN(inst, wui_maps)
|
||||
|
||||
/**
|
||||
* @brief Macro function to construct a list of npcx_wui items by UTIL_LISTIFY
|
||||
*
|
||||
* @param child child index in UTIL_LISTIFY extension.
|
||||
* @param inst instance number for compatible defined in DT_DRV_COMPAT.
|
||||
* @return macro function to construct a npcx_wui structure.
|
||||
*/
|
||||
#define NPCX_DT_WUI_ITEMS_FUNC(child, inst) NPCX_DT_WUI_ITEM_BY_IDX(inst, child)
|
||||
|
||||
/**
|
||||
* @brief Macro function to construct a list of npcx_wui items by UTIL_LISTIFY
|
||||
* func.
|
||||
*
|
||||
* Example devicetree fragment:
|
||||
* / {
|
||||
* uart1: serial@400c4000 {
|
||||
* uart-rx = <&wui_cr_sin1>;
|
||||
* ...
|
||||
* };
|
||||
*
|
||||
* gpio0: gpio@40081000 {
|
||||
* wui-maps = <&wui_io00 &wui_io01 &wui_io02 &wui_io03
|
||||
* &wui_io04 &wui_io05 &wui_io06 &wui_io07>;
|
||||
* ...
|
||||
* };
|
||||
* };
|
||||
*
|
||||
* Example usage:
|
||||
* const struct npcx_wui wui_map = NPCX_DT_PHANDLE_FROM_WUI_NAME(inst, uart_rx);
|
||||
* const struct npcx_wui wui_maps[] = NPCX_DT_WUI_ITEMS_LIST(inst);
|
||||
*
|
||||
* @param inst instance number for compatible defined in DT_DRV_COMPAT.
|
||||
* @return an array of npcx_wui items.
|
||||
*/
|
||||
#define NPCX_DT_WUI_ITEMS_LIST(inst) { \
|
||||
LISTIFY(NPCX_DT_WUI_ITEMS_LEN(inst), \
|
||||
NPCX_DT_WUI_ITEMS_FUNC, (,), \
|
||||
inst) \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get a node from path '/npcx_miwus_map/map_miwu(0/1/2)_groups'
|
||||
*
|
||||
* @param i index of npcx miwu devices
|
||||
* @return node identifier with that path.
|
||||
*/
|
||||
#define NPCX_DT_NODE_FROM_MIWU_MAP(i) DT_PATH(npcx_miwus_int_map, \
|
||||
map_miwu##i##_groups)
|
||||
/**
|
||||
* @brief Get the index prop from parent MIWU device node.
|
||||
*
|
||||
* @param child index in UTIL_LISTIFY extension.
|
||||
* @return 'index' prop value of the node which compatible type is
|
||||
* "nuvoton,npcx-miwu".
|
||||
*/
|
||||
#define NPCX_DT_MIWU_IRQ_TABLE_IDX(child) \
|
||||
DT_PROP(DT_PHANDLE(DT_PARENT(child), parent), index)
|
||||
|
||||
/**
|
||||
* @brief Macro function for DT_FOREACH_CHILD to generate a IRQ_CONNECT
|
||||
* implementation.
|
||||
*
|
||||
* @param child index in UTIL_LISTIFY extension.
|
||||
* @return implementation to initialize interrupts of MIWU groups and enable
|
||||
* them.
|
||||
*/
|
||||
#define NPCX_DT_MIWU_IRQ_CONNECT_IMPL_CHILD_FUNC(child) \
|
||||
NPCX_DT_MIWU_IRQ_CONNECT_IMPL_CHILD_FUNC_OBJ(child);
|
||||
|
||||
#define NPCX_DT_MIWU_IRQ_CONNECT_IMPL_CHILD_FUNC_OBJ(child) \
|
||||
do { \
|
||||
IRQ_CONNECT(DT_PROP(child, irq), \
|
||||
DT_PROP(child, irq_prio), \
|
||||
NPCX_MIWU_ISR_FUNC(NPCX_DT_MIWU_IRQ_TABLE_IDX(child)), \
|
||||
DT_PROP(child, group_mask), \
|
||||
0); \
|
||||
irq_enable(DT_PROP(child, irq)); \
|
||||
} while (false)
|
||||
|
||||
/**
|
||||
* @brief Get a child node from path '/npcx-espi-vws-map/name'.
|
||||
*
|
||||
* @param name a path which name is /npcx-espi-vws-map/'name'.
|
||||
* @return child node identifier with that path.
|
||||
*/
|
||||
#define NPCX_DT_NODE_FROM_VWTABLE(name) DT_CHILD(DT_PATH(npcx_espi_vws_map), \
|
||||
name)
|
||||
|
||||
/**
|
||||
* @brief Get phandle from vw-wui property of child node with that path.
|
||||
*
|
||||
* @param name path which name is /npcx-espi-vws-map/'name'.
|
||||
* @return phandle from "vw-wui" prop of child node with that path.
|
||||
*/
|
||||
#define NPCX_DT_PHANDLE_VW_WUI(name) DT_PHANDLE(NPCX_DT_NODE_FROM_VWTABLE( \
|
||||
name), vw_wui)
|
||||
|
||||
/**
|
||||
* @brief Construct a npcx_wui structure from vw-wui property of a child node
|
||||
* with that path.
|
||||
*
|
||||
* @param name a path which name is /npcx-espi-vws-map/'name'.
|
||||
* @return npcx_wui item with that path.
|
||||
*/
|
||||
#define NPCX_DT_VW_WUI_ITEM(name) \
|
||||
{ \
|
||||
.table = DT_PROP(DT_PHANDLE(NPCX_DT_PHANDLE_VW_WUI(name), miwus), \
|
||||
index),\
|
||||
.group = DT_PHA(NPCX_DT_PHANDLE_VW_WUI(name), miwus, group), \
|
||||
.bit = DT_PHA(NPCX_DT_PHANDLE_VW_WUI(name), miwus, bit), \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Construct a npcx espi device configuration of vw input signal from
|
||||
* a child node with that path.
|
||||
*
|
||||
* @signal vw input signal name.
|
||||
* @param name a path which name is /npcx-espi-vws-map/'name'.
|
||||
* @return npcx_vw_in_config item with that path.
|
||||
*/
|
||||
#define NPCX_DT_VW_IN_CONF(signal, name) \
|
||||
{ \
|
||||
.sig = signal, \
|
||||
.reg_idx = DT_PROP_BY_IDX(NPCX_DT_NODE_FROM_VWTABLE(name), vw_reg, \
|
||||
0), \
|
||||
.bitmask = DT_PROP_BY_IDX(NPCX_DT_NODE_FROM_VWTABLE(name), vw_reg, \
|
||||
1), \
|
||||
.vw_wui = NPCX_DT_VW_WUI_ITEM(name), \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Construct a npcx espi device configuration of vw output signal from
|
||||
* a child node with that path.
|
||||
*
|
||||
* @signal vw output signal name.
|
||||
* @param name a path which name is /npcx-espi-vws-map/'name'.
|
||||
* @return npcx_vw_in_config item with that path.
|
||||
*/
|
||||
#define NPCX_DT_VW_OUT_CONF(signal, name) \
|
||||
{ \
|
||||
.sig = signal, \
|
||||
.reg_idx = DT_PROP_BY_IDX(NPCX_DT_NODE_FROM_VWTABLE(name), vw_reg, \
|
||||
0), \
|
||||
.bitmask = DT_PROP_BY_IDX(NPCX_DT_NODE_FROM_VWTABLE(name), vw_reg, \
|
||||
1), \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Construct a npcx_lvol structure from 'lvol-maps' property at index 'i'.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
* @param prop Low voltage configurations property name. (i.e. 'lvol-maps')
|
||||
* @param idx Property entry index.
|
||||
*/
|
||||
#define NPCX_DT_LVOL_CTRL_NONE \
|
||||
DT_PHA(DT_NODELABEL(lvol_none), lvols, ctrl)
|
||||
|
||||
/**
|
||||
* @brief Length of npcx_lvol structures in 'lvol-maps' property
|
||||
*
|
||||
* @param inst instance number for compatible defined in DT_DRV_COMPAT.
|
||||
* @return length of 'lvol-maps' prop which type is 'phandles'
|
||||
*/
|
||||
#define NPCX_DT_LVOL_ITEMS_LEN(inst) DT_INST_PROP_LEN(inst, lvol_maps)
|
||||
|
||||
/**
|
||||
* @brief Construct a npcx_lvol structure from 'lvol-maps' property at index 'i'.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
* @param prop Low voltage configurations property name. (i.e. 'lvol-maps')
|
||||
* @param idx Property entry index.
|
||||
*/
|
||||
#define NPCX_DT_LVOL_ITEMS_INIT(node_id, prop, idx) \
|
||||
{ \
|
||||
.ctrl = DT_PHA(DT_PROP_BY_IDX(node_id, prop, idx), lvols, ctrl), \
|
||||
.bit = DT_PHA(DT_PROP_BY_IDX(node_id, prop, idx), lvols, bit), \
|
||||
},
|
||||
|
||||
/**
|
||||
* @brief Macro function to construct a list of npcx_lvol items from 'lvol-maps'
|
||||
* property.
|
||||
*
|
||||
* @param inst instance number for compatible defined in DT_DRV_COMPAT.
|
||||
* @return an array of npcx_lvol items.
|
||||
*/
|
||||
#define NPCX_DT_LVOL_ITEMS_LIST(inst) { \
|
||||
DT_FOREACH_PROP_ELEM(DT_DRV_INST(inst), lvol_maps, \
|
||||
NPCX_DT_LVOL_ITEMS_INIT)}
|
||||
|
||||
/**
|
||||
* @brief Check if the host interface type is automatically configured by
|
||||
* booter.
|
||||
*
|
||||
* @return TRUE - if the host interface is configured by booter,
|
||||
* FALSE - otherwise.
|
||||
*/
|
||||
#define NPCX_BOOTER_IS_HIF_TYPE_SET() \
|
||||
DT_PROP(DT_PATH(booter_variant), hif_type_auto)
|
||||
|
||||
/**
|
||||
* @brief Helper macro to get address of system configuration module which is
|
||||
* used by serval peripheral device drivers in npcx series.
|
||||
*
|
||||
* @return base address of system configuration module.
|
||||
*/
|
||||
#define NPCX_SCFG_REG_ADDR DT_REG_ADDR_BY_NAME(DT_NODELABEL(scfg), scfg)
|
||||
|
||||
/**
|
||||
* @brief Helper macro to get address of system glue module which is
|
||||
* used by serval peripheral device drivers in npcx series.
|
||||
*
|
||||
* @return base address of system glue module.
|
||||
*/
|
||||
#define NPCX_GLUE_REG_ADDR DT_REG_ADDR_BY_NAME(DT_NODELABEL(scfg), glue)
|
||||
|
||||
#endif /* _NUVOTON_NPCX_SOC_DT_H_ */
|
||||
34
soc/nuvoton/npcx/common/soc_espi.h
Normal file
34
soc/nuvoton/npcx/common/soc_espi.h
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _NUVOTON_NPCX_SOC_ESPI_H_
|
||||
#define _NUVOTON_NPCX_SOC_ESPI_H_
|
||||
|
||||
#include <zephyr/device.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Turn on all interrupts of eSPI host interface module.
|
||||
*
|
||||
* @param dev Pointer to structure device of eSPI module
|
||||
*/
|
||||
void npcx_espi_enable_interrupts(const struct device *dev);
|
||||
|
||||
/**
|
||||
* @brief Turn off all interrupts of eSPI host interface module.
|
||||
*
|
||||
* @param dev Pointer to structure device of eSPI module
|
||||
*/
|
||||
void npcx_espi_disable_interrupts(const struct device *dev);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _NUVOTON_NPCX_SOC_ESPI_H_ */
|
||||
151
soc/nuvoton/npcx/common/soc_espi_taf.h
Normal file
151
soc/nuvoton/npcx/common/soc_espi_taf.h
Normal file
|
|
@ -0,0 +1,151 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _NUVOTON_NPCX_SOC_ESPI_TAF_H_
|
||||
#define _NUVOTON_NPCX_SOC_ESPI_TAF_H_
|
||||
|
||||
#include <zephyr/device.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Transmit buffer for eSPI TAF transaction on NPCX */
|
||||
/* +-------------+--------------+--------------+---------------+ */
|
||||
/* | Byte 3 | Byte 2 | Byte 1 | Byte 0 | */
|
||||
/* +-------------+--------------+--------------+---------------+ */
|
||||
/* | Length | Tag |Length | Type | PKT_LEN | */
|
||||
/* | [7:0] | |[11:8] | | | */
|
||||
/* +-------------+--------------+--------------+---------------+ */
|
||||
/* | Data 3 | Data 2 | Data 1 | Data 0 | */
|
||||
/* +-------------+--------------+--------------+---------------+ */
|
||||
/* | Data 7 | Data 6 | Data 5 | Data 4 | */
|
||||
/* +-------------+--------------+--------------+---------------+ */
|
||||
/* | ... | ... | ... | ... | */
|
||||
/* +-------------+--------------+--------------+---------------+ */
|
||||
/* | Data 63 | Data 62 | Data 61 | Data 60 | */
|
||||
/* +-------------+--------------+--------------+---------------+ */
|
||||
/* PKT_LEN holds the sum of header (Type, Tag and Length) length */
|
||||
/* and data length */
|
||||
|
||||
/*
|
||||
* NPCX_TAF_CMP_HEADER_LEN is the preamble length of Type, Length
|
||||
* and Tag (i.e. byte 1~byte 3) for flash access completion packet
|
||||
* on NPCX
|
||||
*/
|
||||
#define NPCX_TAF_CMP_HEADER_LEN 3
|
||||
|
||||
/* Successful Completion Without Data */
|
||||
#define CYC_SCS_CMP_WITHOUT_DATA 0x06
|
||||
/* Successful middle Completion With Data */
|
||||
#define CYC_SCS_CMP_WITH_DATA_MIDDLE 0x09
|
||||
/* Successful first Completion With Data */
|
||||
#define CYC_SCS_CMP_WITH_DATA_FIRST 0x0B
|
||||
/* Successful last Completion With Data */
|
||||
#define CYC_SCS_CMP_WITH_DATA_LAST 0x0D
|
||||
/* Successful only Completion With Data */
|
||||
#define CYC_SCS_CMP_WITH_DATA_ONLY 0x0F
|
||||
/* Unsuccessful Completion Without Data */
|
||||
#define CYC_UNSCS_CMP_WITHOUT_DATA 0x08
|
||||
/* Unsuccessful Last Completion Without Data */
|
||||
#define CYC_UNSCS_CMP_WITHOUT_DATA_LAST 0x0C
|
||||
/* Unsuccessful Only Completion Without Data */
|
||||
#define CYC_UNSCS_CMP_WITHOUT_DATA_ONLY 0x0E
|
||||
|
||||
/* Timeout for checking transmit buffer available and no completion was sent */
|
||||
#define NPCX_FLASH_CHK_TIMEOUT 10000
|
||||
|
||||
/* Clear RSTBUFHEADS, FLASH_ACC_TX_AVAIL, and FLASH_ACC_NP_FREE */
|
||||
#define NPCX_FLASHCTL_ACCESS_MASK (~(BIT(NPCX_FLASHCTL_RSTBUFHEADS) | \
|
||||
BIT(NPCX_FLASHCTL_FLASH_NP_FREE) | \
|
||||
BIT(NPCX_FLASHCTL_FLASH_TX_AVAIL)))
|
||||
|
||||
/* Flash Sharing Capability Support */
|
||||
#define NPCX_FLASH_SHARING_CAP_SUPP_CAF 0
|
||||
#define NPCX_FLASH_SHARING_CAP_SUPP_TAF 2
|
||||
#define NPCX_FLASH_SHARING_CAP_SUPP_TAF_AND_CAF 3
|
||||
|
||||
enum NPCX_ESPI_TAF_REQ {
|
||||
NPCX_ESPI_TAF_REQ_READ,
|
||||
NPCX_ESPI_TAF_REQ_WRITE,
|
||||
NPCX_ESPI_TAF_REQ_ERASE,
|
||||
NPCX_ESPI_TAF_REQ_RPMC_OP1,
|
||||
NPCX_ESPI_TAF_REQ_RPMC_OP2,
|
||||
NPCX_ESPI_TAF_REQ_UNKNOWN,
|
||||
};
|
||||
|
||||
/* NPCX_ESPI_TAF_ERASE_BLOCK_SIZE_4KB is default */
|
||||
enum NPCX_ESPI_TAF_ERASE_BLOCK_SIZE {
|
||||
NPCX_ESPI_TAF_ERASE_BLOCK_SIZE_1KB,
|
||||
NPCX_ESPI_TAF_ERASE_BLOCK_SIZE_2KB,
|
||||
NPCX_ESPI_TAF_ERASE_BLOCK_SIZE_4KB,
|
||||
NPCX_ESPI_TAF_ERASE_BLOCK_SIZE_8KB,
|
||||
NPCX_ESPI_TAF_ERASE_BLOCK_SIZE_16KB,
|
||||
NPCX_ESPI_TAF_ERASE_BLOCK_SIZE_32KB,
|
||||
NPCX_ESPI_TAF_ERASE_BLOCK_SIZE_64KB,
|
||||
NPCX_ESPI_TAF_ERASE_BLOCK_SIZE_128KB,
|
||||
};
|
||||
|
||||
/* NPCX_ESPI_TAF_MAX_READ_REQ_64B is default */
|
||||
enum NPCX_ESPI_TAF_MAX_READ_REQ {
|
||||
NPCX_ESPI_TAF_MAX_READ_REQ_64B = 1,
|
||||
NPCX_ESPI_TAF_MAX_READ_REQ_128B,
|
||||
NPCX_ESPI_TAF_MAX_READ_REQ_256B,
|
||||
NPCX_ESPI_TAF_MAX_READ_REQ_512B,
|
||||
NPCX_ESPI_TAF_MAX_READ_REQ_1024B,
|
||||
NPCX_ESPI_TAF_MAX_READ_REQ_2048B,
|
||||
NPCX_ESPI_TAF_MAX_READ_REQ_4096B,
|
||||
};
|
||||
|
||||
/*
|
||||
* The configurations of SPI flash are set in FIU module.
|
||||
* Thus, eSPI TAF driver of NPCX does not need additional hardware configuarations.
|
||||
* Therefore, define an empty structure here to comply with espi_saf.h
|
||||
*/
|
||||
struct espi_saf_hw_cfg {
|
||||
};
|
||||
|
||||
struct espi_saf_pr {
|
||||
uint32_t start;
|
||||
uint32_t end;
|
||||
uint16_t override_r;
|
||||
uint16_t override_w;
|
||||
uint8_t master_bm_we;
|
||||
uint8_t master_bm_rd;
|
||||
uint8_t pr_num;
|
||||
uint8_t flags;
|
||||
};
|
||||
|
||||
struct espi_saf_protection {
|
||||
size_t nregions;
|
||||
const struct espi_saf_pr *pregions;
|
||||
};
|
||||
|
||||
struct espi_taf_npcx_pckt {
|
||||
uint8_t tag;
|
||||
uint8_t *data;
|
||||
};
|
||||
|
||||
struct espi_taf_pckt {
|
||||
uint8_t type;
|
||||
uint8_t tag;
|
||||
uint32_t addr;
|
||||
uint16_t len;
|
||||
uint32_t src[16];
|
||||
};
|
||||
|
||||
struct npcx_taf_head {
|
||||
uint8_t pkt_len;
|
||||
uint8_t type;
|
||||
uint8_t tag_hlen;
|
||||
uint8_t llen;
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
49
soc/nuvoton/npcx/common/soc_gpio.h
Normal file
49
soc/nuvoton/npcx/common/soc_gpio.h
Normal file
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _NUVOTON_NPCX_SOC_GPIO_H_
|
||||
#define _NUVOTON_NPCX_SOC_GPIO_H_
|
||||
|
||||
#include <zephyr/device.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Pin number for each GPIO device */
|
||||
#define NPCX_GPIO_PORT_PIN_NUM 8U
|
||||
|
||||
/**
|
||||
* @brief Get GPIO device instance by port index
|
||||
*
|
||||
* @param port GPIO device index
|
||||
*
|
||||
* @retval Pointer to structure device
|
||||
* @retval NULL Invalid parameter of GPIO port index
|
||||
*/
|
||||
const struct device *npcx_get_gpio_dev(int port);
|
||||
|
||||
/**
|
||||
* @brief Enable the connection between io pads and GPIO instance
|
||||
*
|
||||
* @param dev Pointer to device structure for the gpio driver instance.
|
||||
* @param pin Pin number.
|
||||
*/
|
||||
void npcx_gpio_enable_io_pads(const struct device *dev, int pin);
|
||||
|
||||
/**
|
||||
* @brief Disable the connection between io pads and GPIO instance
|
||||
*
|
||||
* @param dev Pointer to device structure for the gpio driver instance.
|
||||
* @param pin Pin number.
|
||||
*/
|
||||
void npcx_gpio_disable_io_pads(const struct device *dev, int pin);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _NUVOTON_NPCX_SOC_GPIO_H_ */
|
||||
92
soc/nuvoton/npcx/common/soc_host.h
Normal file
92
soc/nuvoton/npcx/common/soc_host.h
Normal file
|
|
@ -0,0 +1,92 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _NUVOTON_NPCX_SOC_HOST_H_
|
||||
#define _NUVOTON_NPCX_SOC_HOST_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <zephyr/device.h>
|
||||
#include <zephyr/drivers/espi.h>
|
||||
#include <zephyr/sys/slist.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Initializes all host sub-modules in Core domain.
|
||||
*
|
||||
* This routine initializes all host sub-modules which HW blocks belong to
|
||||
* Core domain. And it also saves the pointer of eSPI callback list to report
|
||||
* any peripheral events application layer.
|
||||
*
|
||||
* @param dev Pointer to the device structure for the host bus driver instance.
|
||||
* @param callbacks A pointer to the list of espi callback functions.
|
||||
*
|
||||
* @retval 0 If successful.
|
||||
* @retval -EIO if cannot turn on host sub-module source clocks in core domain.
|
||||
*/
|
||||
int npcx_host_init_subs_core_domain(const struct device *host_bus_dev,
|
||||
sys_slist_t *callbacks);
|
||||
|
||||
/**
|
||||
* @brief Initializes all host sub-modules in Host domain.
|
||||
*
|
||||
* This routine initializes all host sub-modules which HW blocks belong to
|
||||
* Host domain. Please notice it must be executed after receiving PLT_RST
|
||||
* de-asserted signal and eSPI peripheral channel is enabled and ready.
|
||||
*/
|
||||
void npcx_host_init_subs_host_domain(void);
|
||||
|
||||
/**
|
||||
* @brief Reads data from a host sub-module which is updated via eSPI.
|
||||
*
|
||||
* This routine provides a generic interface to read a host sub-module which
|
||||
* information was updated by an eSPI transaction through peripheral channel.
|
||||
*
|
||||
* @param op Enum representing opcode for peripheral type and read request.
|
||||
* @param data Parameter to be read from to the host sub-module.
|
||||
*
|
||||
* @retval 0 If successful.
|
||||
* @retval -ENOTSUP if eSPI peripheral is off or not supported.
|
||||
* @retval -EINVAL for unimplemented lpc opcode, but in range.
|
||||
*/
|
||||
int npcx_host_periph_read_request(enum lpc_peripheral_opcode op,
|
||||
uint32_t *data);
|
||||
|
||||
/**
|
||||
* @brief Writes data to a host sub-module which generates an eSPI transaction.
|
||||
*
|
||||
* This routine provides a generic interface to write data to a host sub-module
|
||||
* which triggers an eSPI transaction through peripheral channel.
|
||||
*
|
||||
* @param op Enum representing an opcode for peripheral type and write request.
|
||||
* @param data Represents the parameter passed to the host sub-module.
|
||||
*
|
||||
* @retval 0 If successful.
|
||||
* @retval -ENOTSUP if eSPI peripheral is off or not supported.
|
||||
* @retval -EINVAL for unimplemented lpc opcode, but in range.
|
||||
*/
|
||||
int npcx_host_periph_write_request(enum lpc_peripheral_opcode op,
|
||||
const uint32_t *data);
|
||||
|
||||
/**
|
||||
* @brief Enable host access wake-up interrupt. Usually, it is used to wake up
|
||||
* ec during system is in Modern standby power mode.
|
||||
*/
|
||||
void npcx_host_enable_access_interrupt(void);
|
||||
|
||||
/**
|
||||
* @brief Disable host access wake-up interrupt.
|
||||
*/
|
||||
void npcx_host_disable_access_interrupt(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _NUVOTON_NPCX_SOC_HOST_H_ */
|
||||
230
soc/nuvoton/npcx/common/soc_miwu.h
Normal file
230
soc/nuvoton/npcx/common/soc_miwu.h
Normal file
|
|
@ -0,0 +1,230 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _NUVOTON_NPCX_SOC_MIWU_H_
|
||||
#define _NUVOTON_NPCX_SOC_MIWU_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <zephyr/device.h>
|
||||
#include <zephyr/drivers/gpio.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
enum miwu_table {
|
||||
NPCX_MIWU_TABLE_0,
|
||||
NPCX_MIWU_TABLE_1,
|
||||
NPCX_MIWU_TABLE_2,
|
||||
NPCX_MIWU_TABLE_COUNT
|
||||
};
|
||||
|
||||
enum miwu_group {
|
||||
NPCX_MIWU_GROUP_1,
|
||||
NPCX_MIWU_GROUP_2,
|
||||
NPCX_MIWU_GROUP_3,
|
||||
NPCX_MIWU_GROUP_4,
|
||||
NPCX_MIWU_GROUP_5,
|
||||
NPCX_MIWU_GROUP_6,
|
||||
NPCX_MIWU_GROUP_7,
|
||||
NPCX_MIWU_GROUP_8,
|
||||
NPCX_MIWU_GROUP_COUNT
|
||||
};
|
||||
|
||||
#define NPCX_MIWU_TABLE_NONE NPCX_MIWU_TABLE_COUNT
|
||||
|
||||
/* Interrupt modes supported by npcx miwu modules */
|
||||
enum miwu_int_mode {
|
||||
NPCX_MIWU_MODE_LEVEL,
|
||||
NPCX_MIWU_MODE_EDGE,
|
||||
};
|
||||
|
||||
/* Interrupt trigger modes supported by npcx miwu modules */
|
||||
enum miwu_int_trig {
|
||||
NPCX_MIWU_TRIG_LOW, /** Edge failing or active low detection */
|
||||
NPCX_MIWU_TRIG_HIGH, /** Edge rising or active high detection */
|
||||
NPCX_MIWU_TRIG_BOTH, /** Both edge rising and failing detection */
|
||||
};
|
||||
|
||||
/* NPCX miwu driver callback type */
|
||||
enum {
|
||||
NPCX_MIWU_CALLBACK_GPIO,
|
||||
NPCX_MIWU_CALLBACK_DEV,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief NPCX wake-up input source structure
|
||||
*
|
||||
* Used to indicate a Wake-Up Input source (WUI) belongs to which group and bit
|
||||
* of Multi-Input Wake-Up Unit (MIWU) modules.
|
||||
*/
|
||||
struct npcx_wui {
|
||||
uint8_t table:2; /** A source belongs to which MIWU table. */
|
||||
uint8_t group:3; /** A source belongs to which group of MIWU table. */
|
||||
uint8_t bit:3; /** A source belongs to which bit of MIWU group. */
|
||||
};
|
||||
|
||||
/**
|
||||
* Define npcx miwu driver callback handler signature for wake-up input source
|
||||
* of generic hardware. Its parameters contain the device issued interrupt
|
||||
* and corresponding WUI source.
|
||||
*/
|
||||
typedef void (*miwu_dev_callback_handler_t)(const struct device *source,
|
||||
struct npcx_wui *wui);
|
||||
|
||||
/**
|
||||
* @brief MIWU/GPIO information structure
|
||||
*
|
||||
* It contains both GPIO and MIWU information which is stored in unused field
|
||||
* of struct gpio_port_pins_t since a interested mask of pins is only 8 bits.
|
||||
* Beware the size of such structure must equal struct gpio_port_pins_t.
|
||||
*/
|
||||
struct miwu_io_params {
|
||||
uint8_t pin_mask; /** A mask of pins the callback is interested in. */
|
||||
uint8_t gpio_port; /** GPIO device index */
|
||||
uint8_t cb_type; /** Callback type */
|
||||
struct npcx_wui wui; /** Wake-up input source of GPIO */
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief MIWU/generic device information structure
|
||||
*
|
||||
* It contains the information used for MIWU generic device event. Please notice
|
||||
* the offset of cb_type must be the same as cb_type in struct miwu_io_params.
|
||||
*/
|
||||
struct miwu_dev_params {
|
||||
uint8_t reserve1;
|
||||
uint8_t reserve2;
|
||||
uint8_t cb_type; /** Callback type */
|
||||
struct npcx_wui wui; /** Device instance register callback function */
|
||||
const struct device *source; /** Wake-up input source */
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief MIWU callback structure for a gpio or device input
|
||||
*
|
||||
* Used to register a generic gpio/device callback in the driver instance
|
||||
* callback list. Beware such structure should not be allocated on stack.
|
||||
*
|
||||
* Note: To help setting it, see npcx_miwu_init_dev_callback() and
|
||||
* npcx_miwu_manage_callback() below
|
||||
*/
|
||||
struct miwu_callback {
|
||||
/** Node of single-linked list */
|
||||
sys_snode_t node;
|
||||
union {
|
||||
struct {
|
||||
/** Callback function being called when GPIO event occurred */
|
||||
gpio_callback_handler_t handler;
|
||||
struct miwu_io_params params;
|
||||
} io_cb;
|
||||
|
||||
struct {
|
||||
/** Callback function being called when device event occurred */
|
||||
miwu_dev_callback_handler_t handler;
|
||||
struct miwu_dev_params params;
|
||||
} dev_cb;
|
||||
};
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Enable interrupt of the wake-up input source
|
||||
*
|
||||
* @param A pointer on wake-up input source
|
||||
*/
|
||||
void npcx_miwu_irq_enable(const struct npcx_wui *wui);
|
||||
|
||||
/**
|
||||
* @brief Disable interrupt of the wake-up input source
|
||||
*
|
||||
* @param wui A pointer on wake-up input source
|
||||
*/
|
||||
void npcx_miwu_irq_disable(const struct npcx_wui *wui);
|
||||
|
||||
/**
|
||||
* @brief Connect io to the wake-up input source
|
||||
*
|
||||
* @param wui A pointer on wake-up input source
|
||||
*/
|
||||
void npcx_miwu_io_enable(const struct npcx_wui *wui);
|
||||
|
||||
/**
|
||||
* @brief Disconnect io to the wake-up input source
|
||||
*
|
||||
* @param wui A pointer on wake-up input source
|
||||
*/
|
||||
void npcx_miwu_io_disable(const struct npcx_wui *wui);
|
||||
|
||||
/**
|
||||
* @brief Get interrupt state of the wake-up input source
|
||||
*
|
||||
* @param wui A pointer on wake-up input source
|
||||
*
|
||||
* @retval 0 if interrupt is disabled, otherwise interrupt is enabled
|
||||
*/
|
||||
bool npcx_miwu_irq_get_state(const struct npcx_wui *wui);
|
||||
|
||||
/**
|
||||
* @brief Get & clear interrupt pending bit of the wake-up input source
|
||||
*
|
||||
* @param wui A pointer on wake-up input source
|
||||
*
|
||||
* @retval 1 if interrupt is pending
|
||||
*/
|
||||
bool npcx_miwu_irq_get_and_clear_pending(const struct npcx_wui *wui);
|
||||
|
||||
/**
|
||||
* @brief Configure interrupt type of the wake-up input source
|
||||
*
|
||||
* @param wui Pointer to wake-up input source for configuring
|
||||
* @param mode Interrupt mode supported by NPCX MIWU
|
||||
* @param trig Interrupt trigger mode supported by NPCX MIWU
|
||||
*
|
||||
* @retval 0 If successful
|
||||
* @retval -EINVAL Invalid parameters
|
||||
*/
|
||||
int npcx_miwu_interrupt_configure(const struct npcx_wui *wui,
|
||||
enum miwu_int_mode mode, enum miwu_int_trig trig);
|
||||
|
||||
/**
|
||||
* @brief Function to initialize a struct miwu_callback with gpio properly
|
||||
*
|
||||
* @param callback Pointer to io callback structure for initialization
|
||||
* @param io_wui Pointer to wake-up input IO source
|
||||
* @param port GPIO port issued a callback function
|
||||
*/
|
||||
void npcx_miwu_init_gpio_callback(struct miwu_callback *callback,
|
||||
const struct npcx_wui *io_wui, int port);
|
||||
|
||||
/**
|
||||
* @brief Function to initialize a struct miwu_callback with device properly
|
||||
*
|
||||
* @param callback Pointer to device callback structure for initialization
|
||||
* @param dev_wui Pointer to wake-up input device source
|
||||
* @param handler A function called when its device input event issued
|
||||
* @param source Pointer to device instance issued a callback function
|
||||
*/
|
||||
void npcx_miwu_init_dev_callback(struct miwu_callback *callback,
|
||||
const struct npcx_wui *dev_wui,
|
||||
miwu_dev_callback_handler_t handler,
|
||||
const struct device *source);
|
||||
|
||||
/**
|
||||
* @brief Function to insert or remove a miwu callback from a callback list
|
||||
*
|
||||
* @param callback Pointer to miwu callback structure
|
||||
* @param set A boolean indicating insertion or removal of the callback
|
||||
*
|
||||
* @retval 0 If successful.
|
||||
* @retval -EINVAL Invalid parameters
|
||||
*/
|
||||
int npcx_miwu_manage_callback(struct miwu_callback *cb, bool set);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _NUVOTON_NPCX_SOC_MIWU_H_ */
|
||||
92
soc/nuvoton/npcx/common/soc_pins.h
Normal file
92
soc/nuvoton/npcx/common/soc_pins.h
Normal file
|
|
@ -0,0 +1,92 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _NUVOTON_NPCX_SOC_PINS_H_
|
||||
#define _NUVOTON_NPCX_SOC_PINS_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "reg/reg_def.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NPCX pin-mux configuration structure
|
||||
*
|
||||
* Used to indicate the device's corresponding DEVALT register/bit for
|
||||
* pin-muxing and its polarity to enable alternative functionality.
|
||||
*/
|
||||
struct npcx_alt {
|
||||
uint8_t group;
|
||||
uint8_t bit:3;
|
||||
uint8_t inverted:1;
|
||||
uint8_t reserved:4;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief NPCX low-voltage configuration structure
|
||||
*
|
||||
* Used to indicate the device's corresponding LV_GPIO_CTL register/bit for
|
||||
* low-voltage detection.
|
||||
*/
|
||||
struct npcx_lvol {
|
||||
uint8_t ctrl:5; /** Related register index for low-voltage conf. */
|
||||
uint8_t bit:3; /** Related register bit for low-voltage conf. */
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Select i2c port pads of i2c controller
|
||||
*
|
||||
* @param controller i2c controller device
|
||||
* @param port index for i2c port pads
|
||||
*/
|
||||
void npcx_pinctrl_i2c_port_sel(int controller, int port);
|
||||
|
||||
/**
|
||||
* @brief Force the internal SPI flash write-protect pin (WP) to low level to
|
||||
* protect the flash Status registers.
|
||||
*/
|
||||
int npcx_pinctrl_flash_write_protect_set(void);
|
||||
|
||||
/**
|
||||
* @brief Get write protection status
|
||||
*
|
||||
* @return 1 if write protection is set, 0 otherwise.
|
||||
*/
|
||||
bool npcx_pinctrl_flash_write_protect_is_set(void);
|
||||
|
||||
/**
|
||||
* @brief Enable low-voltage input detection
|
||||
*
|
||||
* @param lvol_ctrl Related register index for low-voltage detection
|
||||
* @param lvol_bit Related register bit for low-voltage detection
|
||||
* @param enable True to enable low-voltage input detection, false to disable.
|
||||
*/
|
||||
void npcx_lvol_set_detect_level(int lvol_ctrl, int lvol_bit, bool enable);
|
||||
|
||||
/**
|
||||
* @brief Get status of low-voltage input detection
|
||||
*
|
||||
* @param lvol_ctrl Related register index for low-voltage detection
|
||||
* @param lvol_bit Related register bit for low-voltage detection
|
||||
* @return True means the low-voltage power supply is enabled, otherwise disabled.
|
||||
*/
|
||||
bool npcx_lvol_get_detect_level(int lvol_ctrl, int lvol_bit);
|
||||
|
||||
/**
|
||||
* @brief Select the host interface type
|
||||
*
|
||||
* @param hif_type host interface type
|
||||
*/
|
||||
void npcx_host_interface_sel(enum npcx_hif_type hif_type);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _NUVOTON_NPCX_SOC_PINS_H_ */
|
||||
28
soc/nuvoton/npcx/common/soc_power.h
Normal file
28
soc/nuvoton/npcx/common/soc_power.h
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _NUVOTON_NPCX_SOC_POWER_H_
|
||||
#define _NUVOTON_NPCX_SOC_POWER_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Disable UART RX wake-up interrupt.
|
||||
*/
|
||||
void npcx_uart_disable_access_interrupt(void);
|
||||
|
||||
/**
|
||||
* @brief Enable UART RX wake-up interrupt.
|
||||
*/
|
||||
void npcx_uart_enable_access_interrupt(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _NUVOTON_NPCX_SOC_POWER_H_ */
|
||||
12
soc/nuvoton/npcx/npcx4/CMakeLists.txt
Normal file
12
soc/nuvoton/npcx/npcx4/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_include_directories(
|
||||
.
|
||||
${ZEPHYR_BASE}/drivers
|
||||
)
|
||||
|
||||
zephyr_sources(
|
||||
soc.c
|
||||
)
|
||||
|
||||
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
|
||||
12
soc/nuvoton/npcx/npcx4/Kconfig
Normal file
12
soc/nuvoton/npcx/npcx4/Kconfig
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
# Nuvoton NPCX4 EC series
|
||||
|
||||
# Copyright (c) 2023 Nuvoton Technology Corporation.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_NPCX4
|
||||
select ARM
|
||||
select CPU_CORTEX_M4
|
||||
select CPU_CORTEX_M_HAS_DWT
|
||||
select CPU_HAS_FPU
|
||||
select CPU_HAS_ARM_MPU
|
||||
select HAS_PM
|
||||
18
soc/nuvoton/npcx/npcx4/Kconfig.defconfig
Normal file
18
soc/nuvoton/npcx/npcx4/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
# Nuvoton Cortex-M4 Embedded Controller
|
||||
|
||||
# Copyright (c) 2023 Nuvoton Technology Corporation.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_NPCX4
|
||||
|
||||
config NUM_IRQS
|
||||
default 128
|
||||
|
||||
config CORTEX_M_SYSTICK
|
||||
default !NPCX_ITIM_TIMER
|
||||
|
||||
config ESPI_TAF_NPCX
|
||||
default y
|
||||
depends on ESPI_SAF
|
||||
|
||||
endif # SOC_SERIES_NPCX4
|
||||
29
soc/nuvoton/npcx/npcx4/Kconfig.soc
Normal file
29
soc/nuvoton/npcx/npcx4/Kconfig.soc
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
# Nuvoton NPCX4 EC series
|
||||
|
||||
# Copyright (c) 2023 Nuvoton Technology Corporation.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_NPCX4
|
||||
bool
|
||||
select SOC_FAMILY_NPCX
|
||||
help
|
||||
Enable support for Nuvoton NPCX4 series
|
||||
|
||||
config SOC_NPCX4M3F
|
||||
bool
|
||||
select SOC_SERIES_NPCX4
|
||||
help
|
||||
NPCX4M3F
|
||||
|
||||
config SOC_NPCX4M8F
|
||||
bool
|
||||
select SOC_SERIES_NPCX4
|
||||
help
|
||||
NPCX4M8F
|
||||
|
||||
config SOC_SERIES
|
||||
default "npcx4" if SOC_SERIES_NPCX4
|
||||
|
||||
config SOC
|
||||
default "npcx4m3f" if SOC_NPCX4M3F
|
||||
default "npcx4m8f" if SOC_NPCX4M8F
|
||||
36
soc/nuvoton/npcx/npcx4/soc.c
Normal file
36
soc/nuvoton/npcx/npcx4/soc.c
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/kernel.h>
|
||||
#include <zephyr/device.h>
|
||||
#include <zephyr/init.h>
|
||||
#include <soc.h>
|
||||
#include <zephyr/logging/log.h>
|
||||
|
||||
LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
|
||||
|
||||
#define NPCX_FIU_INST_INIT(node_id) DT_REG_ADDR(node_id),
|
||||
|
||||
static uintptr_t fiu_insts[] = {
|
||||
DT_FOREACH_STATUS_OKAY(nuvoton_npcx_fiu_qspi, NPCX_FIU_INST_INIT)
|
||||
};
|
||||
|
||||
static int soc_npcx4_init(void)
|
||||
{
|
||||
/*
|
||||
* Make sure UMA_ADDR_SIZE field of UMA_ECTS register is zero in npcx4
|
||||
* series. There should be no address field in UMA mode by default.
|
||||
*/
|
||||
for (int i = 0; i < ARRAY_SIZE(fiu_insts); i++) {
|
||||
struct fiu_reg *const inst = (struct fiu_reg *)(fiu_insts[i]);
|
||||
|
||||
SET_FIELD(inst->UMA_ECTS, NPCX_UMA_ECTS_UMA_ADDR_SIZE, 0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(soc_npcx4_init, PRE_KERNEL_1, 0);
|
||||
60
soc/nuvoton/npcx/npcx4/soc.h
Normal file
60
soc/nuvoton/npcx/npcx4/soc.h
Normal file
|
|
@ -0,0 +1,60 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _NUVOTON_NPCX_SOC_H_
|
||||
#define _NUVOTON_NPCX_SOC_H_
|
||||
|
||||
#include <cmsis_core_m_defaults.h>
|
||||
|
||||
/* NPCX4 SCFG multi-registers */
|
||||
#define NPCX_DEVALT_OFFSET(n) (0x010 + n)
|
||||
#define NPCX_PUPD_EN_OFFSET(n) (0x02b + n)
|
||||
#define NPCX_LV_GPIO_CTL_OFFSET(n) (0x150 + n)
|
||||
#define NPCX_DEVALT_LK_OFFSET(n) (0x210 + n)
|
||||
|
||||
/* NPCX4 MIWU multi-registers */
|
||||
#define NPCX_WKEDG_OFFSET(n) (0x000 + (n * 0x010))
|
||||
#define NPCX_WKAEDG_OFFSET(n) (0x001 + (n * 0x010))
|
||||
#define NPCX_WKMOD_OFFSET(n) (0x002 + (n * 0x010))
|
||||
#define NPCX_WKPND_OFFSET(n) (0x003 + (n * 0x010))
|
||||
#define NPCX_WKPCL_OFFSET(n) (0x004 + (n * 0x010))
|
||||
#define NPCX_WKEN_OFFSET(n) (0x005 + (n * 0x010))
|
||||
#define NPCX_WKST_OFFSET(n) (0x006 + (n * 0x010))
|
||||
#define NPCX_WKINEN_OFFSET(n) (0x007 + (n * 0x010))
|
||||
|
||||
/* NPCX4 ADC multi-registers */
|
||||
#define NPCX_CHNDAT_OFFSET(n) (0x040 + n * 2)
|
||||
#define NPCX_THRCTL_OFFSET(n) (0x080 + n * 2)
|
||||
#define NPCX_THEN_OFFSET 0x090
|
||||
#define THEN(base) (*(volatile uint16_t *)(base + NPCX_THEN_OFFSET))
|
||||
|
||||
/* NPCX4 ADC register fields */
|
||||
#define NPCX_THRCTL_L_H 15
|
||||
#define NPCX_THRCTL_CHNSEL FIELD(10, 5)
|
||||
#define NPCX_THRCTL_THRVAL FIELD(0, 10)
|
||||
|
||||
/* NPCX4 FIU register fields */
|
||||
#define NPCX_FIU_EXT_CFG_SPI1_2DEV 6
|
||||
|
||||
/* NPCX4 supported group mask of DEVALT_LK */
|
||||
#define NPCX_DEVALT_LK_GROUP_MASK \
|
||||
(BIT(0) | BIT(2) | BIT(3) | BIT(4) | \
|
||||
BIT(5) | BIT(6) | BIT(11) | BIT(13) | \
|
||||
BIT(15) | BIT(16) | BIT(17) | BIT(18) | \
|
||||
BIT(19) | BIT(21)) /* DEVALT0_LK - DEVALTN_LK */
|
||||
|
||||
/* NPCX4 Clock Configuration */
|
||||
#define MAX_OFMCLK 120000000
|
||||
|
||||
#include <reg/reg_access.h>
|
||||
#include <reg/reg_def.h>
|
||||
#include <soc_dt.h>
|
||||
#include <soc_clock.h>
|
||||
#include <soc_espi_taf.h>
|
||||
#include <soc_pins.h>
|
||||
#include <soc_power.h>
|
||||
|
||||
#endif /* _NUVOTON_NPCX_SOC_H_ */
|
||||
17
soc/nuvoton/npcx/npcx7/CMakeLists.txt
Normal file
17
soc/nuvoton/npcx/npcx7/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_include_directories(
|
||||
.
|
||||
${ZEPHYR_BASE}/drivers
|
||||
)
|
||||
|
||||
zephyr_sources(
|
||||
soc.c
|
||||
)
|
||||
|
||||
zephyr_sources_ifdef(
|
||||
CONFIG_ARM_MPU
|
||||
mpu_regions.c
|
||||
)
|
||||
|
||||
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
|
||||
13
soc/nuvoton/npcx/npcx7/Kconfig
Normal file
13
soc/nuvoton/npcx/npcx7/Kconfig
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
# Nuvoton Cortex-M4 Embedded Controller NPCX7 series
|
||||
|
||||
# Copyright (c) 2020 Nuvoton Technology Corporation.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_NPCX7
|
||||
select ARM
|
||||
select CPU_CORTEX_M4
|
||||
select CPU_CORTEX_M_HAS_DWT
|
||||
select CPU_HAS_FPU
|
||||
select CPU_HAS_ARM_MPU
|
||||
select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
|
||||
select HAS_PM
|
||||
14
soc/nuvoton/npcx/npcx7/Kconfig.defconfig
Normal file
14
soc/nuvoton/npcx/npcx7/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
# Nuvoton Cortex-M4 Embedded Controller
|
||||
|
||||
# Copyright (c) 2020 Nuvoton Technology Corporation.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_NPCX7
|
||||
|
||||
config NUM_IRQS
|
||||
default 64
|
||||
|
||||
config CORTEX_M_SYSTICK
|
||||
default !NPCX_ITIM_TIMER
|
||||
|
||||
endif # SOC_SERIES_NPCX7
|
||||
36
soc/nuvoton/npcx/npcx7/Kconfig.soc
Normal file
36
soc/nuvoton/npcx/npcx7/Kconfig.soc
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
# Nuvoton Cortex-M4 Embedded Controller NPCX7 series
|
||||
|
||||
# Copyright (c) 2020 Nuvoton Technology Corporation.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_NPCX7
|
||||
bool
|
||||
select SOC_FAMILY_NPCX
|
||||
help
|
||||
Enable support for Nuvoton NPCX7 series
|
||||
|
||||
config SOC_NPCX7M6FB
|
||||
bool
|
||||
select SOC_SERIES_NPCX7
|
||||
help
|
||||
NPCX7M6FB
|
||||
|
||||
config SOC_NPCX7M6FC
|
||||
bool
|
||||
select SOC_SERIES_NPCX7
|
||||
help
|
||||
NPCX7M6FC
|
||||
|
||||
config SOC_NPCX7M7FC
|
||||
bool
|
||||
select SOC_SERIES_NPCX7
|
||||
help
|
||||
NPCX7M7FC
|
||||
|
||||
config SOC_SERIES
|
||||
default "npcx7" if SOC_SERIES_NPCX7
|
||||
|
||||
config SOC
|
||||
default "npcx7m6fb" if SOC_NPCX7M6FB
|
||||
default "npcx7m6fc" if SOC_NPCX7M6FC
|
||||
default "npcx7m7fc" if SOC_NPCX7M7FC
|
||||
26
soc/nuvoton/npcx/npcx7/mpu_regions.c
Normal file
26
soc/nuvoton/npcx/npcx7/mpu_regions.c
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* Copyright (c) 2021 The Chromium OS Authors
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
|
||||
|
||||
static const struct arm_mpu_region mpu_regions[] = {
|
||||
MPU_REGION_ENTRY("FLASH_0_0",
|
||||
CONFIG_FLASH_BASE_ADDRESS & -KB(256),
|
||||
REGION_FLASH_ATTR(REGION_256K)),
|
||||
#if CONFIG_FLASH_SIZE > 256
|
||||
MPU_REGION_ENTRY("FLASH_0_1",
|
||||
(CONFIG_FLASH_BASE_ADDRESS + KB(256)) & -KB(256),
|
||||
REGION_FLASH_ATTR(REGION_256K)),
|
||||
#endif
|
||||
MPU_REGION_ENTRY("SRAM_0",
|
||||
CONFIG_SRAM_BASE_ADDRESS,
|
||||
REGION_RAM_ATTR(REGION_SRAM_SIZE)),
|
||||
};
|
||||
|
||||
const struct arm_mpu_config mpu_config = {
|
||||
.num_regions = ARRAY_SIZE(mpu_regions),
|
||||
.mpu_regions = mpu_regions,
|
||||
};
|
||||
29
soc/nuvoton/npcx/npcx7/soc.c
Normal file
29
soc/nuvoton/npcx/npcx7/soc.c
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/kernel.h>
|
||||
#include <zephyr/device.h>
|
||||
#include <zephyr/init.h>
|
||||
#include <soc.h>
|
||||
#include <zephyr/logging/log.h>
|
||||
|
||||
LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
|
||||
|
||||
static int soc_npcx7_init(void)
|
||||
{
|
||||
struct scfg_reg *inst_scfg = (struct scfg_reg *)
|
||||
DT_REG_ADDR_BY_NAME(DT_NODELABEL(scfg), scfg);
|
||||
|
||||
/*
|
||||
* Set bit 7 of DEVCNT again for npcx7 series. Please see Errata
|
||||
* for more information. It will be fixed in next chip.
|
||||
*/
|
||||
inst_scfg->DEVCNT |= BIT(7);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(soc_npcx7_init, PRE_KERNEL_1, 0);
|
||||
52
soc/nuvoton/npcx/npcx7/soc.h
Normal file
52
soc/nuvoton/npcx/npcx7/soc.h
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _NUVOTON_NPCX_SOC_H_
|
||||
#define _NUVOTON_NPCX_SOC_H_
|
||||
|
||||
#include <cmsis_core_m_defaults.h>
|
||||
|
||||
/* NPCX7 SCFG multi-registers offset */
|
||||
#define NPCX_DEVALT_OFFSET(n) (0x010 + n)
|
||||
#define NPCX_PUPD_EN_OFFSET(n) (0x028 + n)
|
||||
#define NPCX_LV_GPIO_CTL_OFFSET(n) ((n < 5) ? (0x02a + n) : (0x021 + n))
|
||||
#define NPCX_DEVALT_LK_OFFSET(n) (0x210 + n)
|
||||
|
||||
/* NPCX7 MIWU multi-registers offset */
|
||||
#define NPCX_WKEDG_OFFSET(n) (0x000 + (n * 2) + ((n < 5) ? 0 : 0x01e))
|
||||
#define NPCX_WKAEDG_OFFSET(n) (0x001 + (n * 2) + ((n < 5) ? 0 : 0x01e))
|
||||
#define NPCX_WKMOD_OFFSET(n) (0x070 + n)
|
||||
#define NPCX_WKPND_OFFSET(n) (0x00a + (n * 4) + ((n < 5) ? 0 : 0x010))
|
||||
#define NPCX_WKPCL_OFFSET(n) (0x00c + (n * 4) + ((n < 5) ? 0 : 0x010))
|
||||
#define NPCX_WKEN_OFFSET(n) (0x01e + (n * 2) + ((n < 5) ? 0 : 0x012))
|
||||
#define NPCX_WKINEN_OFFSET(n) (0x01f + (n * 2) + ((n < 5) ? 0 : 0x012))
|
||||
|
||||
/* NPCX7 ADC multi-registers offset */
|
||||
#define NPCX_CHNDAT_OFFSET(n) (0x040 + (n * 2))
|
||||
#define NPCX_THRCTL_OFFSET(n) (0x014 + (n * 2))
|
||||
|
||||
/* NPCX7 ADC register fields */
|
||||
#define NPCX_THRCTL_THEN 15
|
||||
#define NPCX_THRCTL_L_H 14
|
||||
#define NPCX_THRCTL_CHNSEL FIELD(10, 4)
|
||||
#define NPCX_THRCTL_THRVAL FIELD(0, 10)
|
||||
|
||||
/* NPCX7 supported group mask of DEVALT_LK */
|
||||
#define NPCX_DEVALT_LK_GROUP_MASK \
|
||||
(BIT(0) | BIT(2) | BIT(3) | BIT(4) | \
|
||||
BIT(6) | BIT(11) | BIT(15)) /* DEVALT0_LK - DEVALTF_LK */
|
||||
|
||||
/* NPCX7 Clock configuration */
|
||||
#define MAX_OFMCLK 100000000
|
||||
|
||||
#include <reg/reg_access.h>
|
||||
#include <reg/reg_def.h>
|
||||
#include <soc_dt.h>
|
||||
#include <soc_clock.h>
|
||||
#include <soc_pins.h>
|
||||
#include <soc_power.h>
|
||||
|
||||
#endif /* _NUVOTON_NPCX_SOC_H_ */
|
||||
8
soc/nuvoton/npcx/npcx9/CMakeLists.txt
Normal file
8
soc/nuvoton/npcx/npcx9/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_include_directories(
|
||||
.
|
||||
${ZEPHYR_BASE}/drivers
|
||||
)
|
||||
|
||||
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
|
||||
13
soc/nuvoton/npcx/npcx9/Kconfig
Normal file
13
soc/nuvoton/npcx/npcx9/Kconfig
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
# Nuvoton Cortex-M4 Embedded Controller NPCX9 series
|
||||
|
||||
# Copyright (c) 2021 Nuvoton Technology Corporation.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_NPCX9
|
||||
select ARM
|
||||
select CPU_CORTEX_M4
|
||||
select CPU_CORTEX_M_HAS_DWT
|
||||
select CPU_HAS_FPU
|
||||
select CPU_HAS_ARM_MPU
|
||||
select SOC_FAMILY_NPCX
|
||||
select HAS_PM
|
||||
14
soc/nuvoton/npcx/npcx9/Kconfig.defconfig
Normal file
14
soc/nuvoton/npcx/npcx9/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
# Nuvoton Cortex-M4 Embedded Controller
|
||||
|
||||
# Copyright (c) 2021 Nuvoton Technology Corporation.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_NPCX9
|
||||
|
||||
config NUM_IRQS
|
||||
default 64
|
||||
|
||||
config CORTEX_M_SYSTICK
|
||||
default !NPCX_ITIM_TIMER
|
||||
|
||||
endif # SOC_SERIES_NPCX9
|
||||
43
soc/nuvoton/npcx/npcx9/Kconfig.soc
Normal file
43
soc/nuvoton/npcx/npcx9/Kconfig.soc
Normal file
|
|
@ -0,0 +1,43 @@
|
|||
# Nuvoton Cortex-M4 Embedded Controller NPCX9 series
|
||||
|
||||
# Copyright (c) 2021 Nuvoton Technology Corporation.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_NPCX9
|
||||
bool
|
||||
select SOC_FAMILY_NPCX
|
||||
help
|
||||
Enable support for Nuvoton NPCX9 series
|
||||
|
||||
config SOC_NPCX9M3F
|
||||
bool
|
||||
select SOC_SERIES_NPCX9
|
||||
help
|
||||
NPCX9M3F
|
||||
|
||||
config SOC_NPCX9M6F
|
||||
bool
|
||||
select SOC_SERIES_NPCX9
|
||||
help
|
||||
NPCX9M6F
|
||||
|
||||
config SOC_NPCX9M7F
|
||||
bool
|
||||
select SOC_SERIES_NPCX9
|
||||
help
|
||||
NPCX9M7F
|
||||
|
||||
config SOC_NPCX9MFP
|
||||
bool
|
||||
select SOC_SERIES_NPCX9
|
||||
help
|
||||
NPCX9MFP
|
||||
|
||||
config SOC_SERIES
|
||||
default "npcx9" if SOC_SERIES_NPCX9
|
||||
|
||||
config SOC
|
||||
default "npcx9m3f" if SOC_NPCX9M3F
|
||||
default "npcx9m6f" if SOC_NPCX9M6F
|
||||
default "npcx9m7f" if SOC_NPCX9M7F
|
||||
default "npcx9mfp" if SOC_NPCX9MFP
|
||||
57
soc/nuvoton/npcx/npcx9/soc.h
Normal file
57
soc/nuvoton/npcx/npcx9/soc.h
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _NUVOTON_NPCX_SOC_H_
|
||||
#define _NUVOTON_NPCX_SOC_H_
|
||||
|
||||
#include <cmsis_core_m_defaults.h>
|
||||
|
||||
/* NPCX9 SCFG multi-registers */
|
||||
#define NPCX_DEVALT_OFFSET(n) (0x010 + n)
|
||||
#define NPCX_PUPD_EN_OFFSET(n) (0x028 + n)
|
||||
#define NPCX_LV_GPIO_CTL_OFFSET(n) ((n < 5) ? (0x02a + n) : (0x021 + n))
|
||||
#define NPCX_DEVALT_LK_OFFSET(n) (0x210 + n)
|
||||
|
||||
/* NPCX9 MIWU multi-registers */
|
||||
#define NPCX_WKEDG_OFFSET(n) (0x000 + (n * 0x010))
|
||||
#define NPCX_WKAEDG_OFFSET(n) (0x001 + (n * 0x010))
|
||||
#define NPCX_WKMOD_OFFSET(n) (0x002 + (n * 0x010))
|
||||
#define NPCX_WKPND_OFFSET(n) (0x003 + (n * 0x010))
|
||||
#define NPCX_WKPCL_OFFSET(n) (0x004 + (n * 0x010))
|
||||
#define NPCX_WKEN_OFFSET(n) (0x005 + (n * 0x010))
|
||||
#define NPCX_WKST_OFFSET(n) (0x006 + (n * 0x010))
|
||||
#define NPCX_WKINEN_OFFSET(n) (0x007 + (n * 0x010))
|
||||
|
||||
/* NPCX9 ADC multi-registers */
|
||||
#define NPCX_CHNDAT_OFFSET(n) (0x040 + (n * 2))
|
||||
#define NPCX_THRCTL_OFFSET(n) (0x060 + (n * 2))
|
||||
|
||||
/* NPCX9 ADC register fields */
|
||||
#define NPCX_THRCTL_THEN 15
|
||||
#define NPCX_THRCTL_L_H 14
|
||||
#define NPCX_THRCTL_CHNSEL FIELD(10, 4)
|
||||
#define NPCX_THRCTL_THRVAL FIELD(0, 10)
|
||||
|
||||
/* NPCX9 FIU register fields */
|
||||
#define NPCX_FIU_EXT_CFG_SPI1_2DEV 7
|
||||
|
||||
/* NPCX9 supported group mask of DEVALT_LK */
|
||||
#define NPCX_DEVALT_LK_GROUP_MASK \
|
||||
(BIT(0) | BIT(2) | BIT(3) | BIT(4) | \
|
||||
BIT(5) | BIT(6) | BIT(11) | BIT(13) | \
|
||||
BIT(15) | BIT(16) | BIT(17) | BIT(18)) /* DEVALT0_LK - DEVALTJ_LK */
|
||||
|
||||
/* NPCX9 Clock configuration and limitation */
|
||||
#define MAX_OFMCLK 100000000
|
||||
|
||||
#include <reg/reg_access.h>
|
||||
#include <reg/reg_def.h>
|
||||
#include <soc_dt.h>
|
||||
#include <soc_clock.h>
|
||||
#include <soc_pins.h>
|
||||
#include <soc_power.h>
|
||||
|
||||
#endif /* _NUVOTON_NPCX_SOC_H_ */
|
||||
18
soc/nuvoton/npcx/soc.yml
Normal file
18
soc/nuvoton/npcx/soc.yml
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
family:
|
||||
- name: npcx
|
||||
series:
|
||||
- name: npcx4
|
||||
socs:
|
||||
- name: npcx4m3f
|
||||
- name: npcx4m8f
|
||||
- name: npcx7
|
||||
socs:
|
||||
- name: npcx7m6fb
|
||||
- name: npcx7m6fc
|
||||
- name: npcx7m7fc
|
||||
- name: npcx9
|
||||
socs:
|
||||
- name: npcx9m3f
|
||||
- name: npcx9m6f
|
||||
- name: npcx9m7f
|
||||
- name: npcx9mfp
|
||||
8
soc/nuvoton/numaker/CMakeLists.txt
Normal file
8
soc/nuvoton/numaker/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
# Copyright (c) 2023 Nuvoton Technology Corporation.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# This is for access to pinctrl macros
|
||||
zephyr_include_directories(common)
|
||||
|
||||
add_subdirectory(${SOC_SERIES})
|
||||
12
soc/nuvoton/numaker/Kconfig
Normal file
12
soc/nuvoton/numaker/Kconfig
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
# Copyright (c) 2023 Nuvoton Technology Corporation.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_FAMILY_NUMAKER
|
||||
select PLATFORM_SPECIFIC_INIT
|
||||
|
||||
if SOC_FAMILY_NUMAKER
|
||||
|
||||
rsource "*/Kconfig"
|
||||
|
||||
endif # SOC_FAMILY_NUMAKER
|
||||
12
soc/nuvoton/numaker/Kconfig.defconfig
Normal file
12
soc/nuvoton/numaker/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
# Copyright (c) 2023 Nuvoton Technology Corporation.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_FAMILY_NUMAKER
|
||||
|
||||
rsource "*/Kconfig.defconfig"
|
||||
|
||||
config RESET
|
||||
default y
|
||||
|
||||
endif
|
||||
11
soc/nuvoton/numaker/Kconfig.soc
Normal file
11
soc/nuvoton/numaker/Kconfig.soc
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
# Copyright (c) 2023 Nuvoton Technology Corporation.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_FAMILY_NUMAKER
|
||||
bool
|
||||
|
||||
config SOC_FAMILY
|
||||
default "numaker" if SOC_FAMILY_NUMAKER
|
||||
|
||||
rsource "*/Kconfig.soc"
|
||||
48
soc/nuvoton/numaker/common/pinctrl_soc.h
Normal file
48
soc/nuvoton/numaker/common/pinctrl_soc.h
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _NUVOTON_NUMAKER_PINCTRL_SOC_H_
|
||||
#define _NUVOTON_NUMAKER_PINCTRL_SOC_H_
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#define PORT_INDEX(pinmux) (((pinmux)&0xF0000000) >> 28)
|
||||
#define PIN_INDEX(pinmux) (((pinmux)&0x0F000000) >> 24)
|
||||
#define MFP_CFG(pinmux) (((pinmux)&0x000000FF) << ((PIN_INDEX(pinmux) % 4) * 8))
|
||||
#define NU_MFP_POS(pinindex) ((pinindex % 4) * 8)
|
||||
#define NU_MFP_MASK(pinindex) (0x1f << NU_MFP_POS(pinindex))
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct pinctrl_soc_pin_t {
|
||||
uint32_t pin_mux;
|
||||
uint32_t open_drain: 1;
|
||||
uint32_t schmitt_enable: 1;
|
||||
uint32_t slew_rate: 2;
|
||||
} pinctrl_soc_pin_t;
|
||||
|
||||
#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
|
||||
{ \
|
||||
.pin_mux = DT_PROP_BY_IDX(node_id, prop, idx), \
|
||||
.open_drain = DT_PROP(node_id, drive_open_drain), \
|
||||
.schmitt_enable = DT_PROP(node_id, input_schmitt_enable), \
|
||||
.slew_rate = DT_ENUM_IDX(node_id, slew_rate), \
|
||||
},
|
||||
|
||||
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
|
||||
{ \
|
||||
DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \
|
||||
Z_PINCTRL_STATE_PIN_INIT) \
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _NUVOTON_NUMAKER_PINCTRL_SOC_H_ */
|
||||
9
soc/nuvoton/numaker/m46x/CMakeLists.txt
Normal file
9
soc/nuvoton/numaker/m46x/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
# Copyright (c) 2023 Nuvoton Technology Corporation.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_sources(soc.c)
|
||||
|
||||
zephyr_include_directories(.)
|
||||
|
||||
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
|
||||
14
soc/nuvoton/numaker/m46x/Kconfig
Normal file
14
soc/nuvoton/numaker/m46x/Kconfig
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
# Copyright (c) 2023 Nuvoton Technology Corporation.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_M46X
|
||||
select ARM
|
||||
select CPU_CORTEX_M4
|
||||
select CPU_CORTEX_M_HAS_DWT
|
||||
select CPU_HAS_FPU
|
||||
select CPU_HAS_ARM_MPU
|
||||
select CORTEX_M_SYSTICK if SYS_CLOCK_EXISTS
|
||||
|
||||
config SOC_M467
|
||||
select HAS_NUMAKER_HAL
|
||||
9
soc/nuvoton/numaker/m46x/Kconfig.defconfig
Normal file
9
soc/nuvoton/numaker/m46x/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
# Copyright (c) 2023 Nuvoton Technology Corporation.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_M46X
|
||||
|
||||
rsource "Kconfig.defconfig.m46*"
|
||||
|
||||
endif # SOC_SERIES_M46X
|
||||
10
soc/nuvoton/numaker/m46x/Kconfig.defconfig.m467
Normal file
10
soc/nuvoton/numaker/m46x/Kconfig.defconfig.m467
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
# Copyright (c) 2023 Nuvoton Technology Corporation.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_M467
|
||||
|
||||
config NUM_IRQS
|
||||
default 127
|
||||
|
||||
endif # SOC_M467
|
||||
19
soc/nuvoton/numaker/m46x/Kconfig.soc
Normal file
19
soc/nuvoton/numaker/m46x/Kconfig.soc
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
# Copyright (c) 2023 Nuvoton Technology Corporation.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_M46X
|
||||
bool
|
||||
select SOC_FAMILY_NUMAKER
|
||||
help
|
||||
Enable support for Nuvoton M46X MCU series
|
||||
|
||||
config SOC_M467
|
||||
bool
|
||||
select SOC_SERIES_M46X
|
||||
|
||||
config SOC_SERIES
|
||||
default "m46x" if SOC_SERIES_M46X
|
||||
|
||||
config SOC
|
||||
default "m467" if SOC_M467
|
||||
86
soc/nuvoton/numaker/m46x/soc.c
Normal file
86
soc/nuvoton/numaker/m46x/soc.c
Normal file
|
|
@ -0,0 +1,86 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/drivers/clock_control/clock_control_numaker.h>
|
||||
/* Hardware and starter kit includes. */
|
||||
#include <NuMicro.h>
|
||||
|
||||
void z_arm_platform_init(void)
|
||||
{
|
||||
SystemInit();
|
||||
|
||||
/* Unlock protected registers */
|
||||
SYS_UnlockReg();
|
||||
|
||||
/*
|
||||
* -------------------
|
||||
* Init System Clock
|
||||
* -------------------
|
||||
*/
|
||||
|
||||
#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), hxt)
|
||||
/* Enable/disable 4~24 MHz external crystal oscillator (HXT) */
|
||||
if (DT_ENUM_IDX(DT_NODELABEL(scc), hxt) == NUMAKER_SCC_CLKSW_ENABLE) {
|
||||
CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
|
||||
/* Wait for HXT clock ready */
|
||||
CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
|
||||
} else if (DT_ENUM_IDX(DT_NODELABEL(scc), hxt) == NUMAKER_SCC_CLKSW_DISABLE) {
|
||||
CLK_DisableXtalRC(CLK_PWRCTL_HXTEN_Msk);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), lxt)
|
||||
/* Enable/disable 32.768 kHz low-speed external crystal oscillator (LXT) */
|
||||
if (DT_ENUM_IDX(DT_NODELABEL(scc), lxt) == NUMAKER_SCC_CLKSW_ENABLE) {
|
||||
CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk);
|
||||
/* Wait for LXT clock ready */
|
||||
CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk);
|
||||
} else if (DT_ENUM_IDX(DT_NODELABEL(scc), lxt) == NUMAKER_SCC_CLKSW_DISABLE) {
|
||||
CLK_DisableXtalRC(CLK_PWRCTL_LXTEN_Msk);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Enable 12 MHz high-speed internal RC oscillator (HIRC) */
|
||||
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
|
||||
/* Wait for HIRC clock ready */
|
||||
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
|
||||
|
||||
/* Enable 10 KHz low-speed internal RC oscillator (LIRC) */
|
||||
CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk);
|
||||
/* Wait for LIRC clock ready */
|
||||
CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
|
||||
|
||||
#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), hirc48)
|
||||
/* Enable/disable 48 MHz high-speed internal RC oscillator (HIRC48) */
|
||||
if (DT_ENUM_IDX(DT_NODELABEL(scc), hirc48) == NUMAKER_SCC_CLKSW_ENABLE) {
|
||||
CLK_EnableXtalRC(CLK_PWRCTL_HIRC48EN_Msk);
|
||||
/* Wait for HIRC48 clock ready */
|
||||
CLK_WaitClockReady(CLK_STATUS_HIRC48STB_Msk);
|
||||
} else if (DT_ENUM_IDX(DT_NODELABEL(scc), hirc48) == NUMAKER_SCC_CLKSW_DISABLE) {
|
||||
CLK_DisableXtalRC(CLK_PWRCTL_HIRC48EN_Msk);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), clk_pclkdiv)
|
||||
/* Set CLK_PCLKDIV register on request */
|
||||
CLK->PCLKDIV = DT_PROP(DT_NODELABEL(scc), clk_pclkdiv);
|
||||
#endif
|
||||
|
||||
#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), core_clock)
|
||||
/* Set core clock (HCLK) on request */
|
||||
CLK_SetCoreClock(DT_PROP(DT_NODELABEL(scc), core_clock));
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Update System Core Clock
|
||||
* User can use SystemCoreClockUpdate() to calculate SystemCoreClock.
|
||||
*/
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
/* Lock protected registers */
|
||||
SYS_LockReg();
|
||||
}
|
||||
13
soc/nuvoton/numaker/m46x/soc.h
Normal file
13
soc/nuvoton/numaker/m46x/soc.h
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_SOC_ARM_NUVOTON_M46X_SOC_H_
|
||||
#define ZEPHYR_SOC_ARM_NUVOTON_M46X_SOC_H_
|
||||
|
||||
/* Hardware and starter kit includes. */
|
||||
#include <NuMicro.h>
|
||||
|
||||
#endif /* ZEPHYR_SOC_ARM_NUVOTON_M46X_SOC_H_*/
|
||||
6
soc/nuvoton/numaker/soc.yml
Normal file
6
soc/nuvoton/numaker/soc.yml
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
family:
|
||||
- name: numaker
|
||||
series:
|
||||
- name: m46x
|
||||
socs:
|
||||
- name: m467
|
||||
9
soc/nuvoton/numicro/CMakeLists.txt
Normal file
9
soc/nuvoton/numicro/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
# Copyright (c) 2020 Linumiz
|
||||
# Author: Saravanan Sekar <saravanan@linumiz.com>
|
||||
|
||||
add_subdirectory(${SOC_SERIES})
|
||||
|
||||
# This is for access to pinctrl macros
|
||||
zephyr_include_directories(common)
|
||||
13
soc/nuvoton/numicro/Kconfig
Normal file
13
soc/nuvoton/numicro/Kconfig
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
# Copyright (c) 2020 Linumiz
|
||||
# Author: Saravanan Sekar <saravanan@linumiz.com>
|
||||
|
||||
config SOC_FAMILY_NUMICRO
|
||||
select PLATFORM_SPECIFIC_INIT
|
||||
|
||||
if SOC_FAMILY_NUMICRO
|
||||
|
||||
rsource "*/Kconfig"
|
||||
|
||||
endif # SOC_FAMILY_NUMICRO
|
||||
10
soc/nuvoton/numicro/Kconfig.defconfig
Normal file
10
soc/nuvoton/numicro/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
# Copyright (c) 2020 Linumiz
|
||||
# Author: Saravanan Sekar <saravanan@linumiz.com>
|
||||
|
||||
if SOC_FAMILY_NUMICRO
|
||||
|
||||
rsource "*/Kconfig.defconfig"
|
||||
|
||||
endif # SOC_FAMILY_NUMICRO
|
||||
12
soc/nuvoton/numicro/Kconfig.soc
Normal file
12
soc/nuvoton/numicro/Kconfig.soc
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
# Copyright (c) 2020 Linumiz
|
||||
# Author: Saravanan Sekar <saravanan@linumiz.com>
|
||||
|
||||
config SOC_FAMILY_NUMICRO
|
||||
bool
|
||||
|
||||
config SOC_FAMILY
|
||||
default "numicro" if SOC_FAMILY_NUMICRO
|
||||
|
||||
rsource "*/Kconfig.soc"
|
||||
52
soc/nuvoton/numicro/common/pinctrl_soc.h
Normal file
52
soc/nuvoton/numicro/common/pinctrl_soc.h
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* Copyright (c) 2022 SEAL AG
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_SOC_ARM_NUVOTON_NUMICRO_COMMON_PINCTRL_SOC_H_
|
||||
#define ZEPHYR_SOC_ARM_NUVOTON_NUMICRO_COMMON_PINCTRL_SOC_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include <zephyr/types.h>
|
||||
#include <zephyr/dt-bindings/gpio/numicro-gpio.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct pinctrl_soc_pin {
|
||||
uint32_t pinmux : 12;
|
||||
uint32_t pull_down : 1;
|
||||
uint32_t pull_up : 1;
|
||||
uint32_t open_drain : 1;
|
||||
uint32_t schmitt_trigger : 1;
|
||||
uint32_t slew_rate : 2;
|
||||
uint32_t input_disable : 1;
|
||||
uint32_t input_debounce : 1;
|
||||
};
|
||||
|
||||
typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
|
||||
|
||||
#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
|
||||
{ \
|
||||
.pinmux = DT_PROP_BY_IDX(node_id, prop, idx), \
|
||||
.pull_down = DT_PROP(node_id, bias_pull_down), \
|
||||
.pull_up = DT_PROP(node_id, bias_pull_up), \
|
||||
.open_drain = DT_PROP(node_id, drive_open_drain), \
|
||||
.schmitt_trigger = DT_PROP(node_id, input_schmitt_enable),\
|
||||
.slew_rate = DT_ENUM_IDX(node_id, slew_rate), \
|
||||
.input_disable = DT_PROP(node_id, input_disable), \
|
||||
.input_debounce = DT_PROP(node_id, input_debounce), \
|
||||
},
|
||||
|
||||
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
|
||||
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
|
||||
DT_FOREACH_PROP_ELEM, pinmux, \
|
||||
Z_PINCTRL_STATE_PIN_INIT)}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ZEPHYR_SOC_ARM_NUVOTON_NUMICRO_COMMON_PINCTRL_SOC_H_ */
|
||||
10
soc/nuvoton/numicro/m48x/CMakeLists.txt
Normal file
10
soc/nuvoton/numicro/m48x/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
# Copyright (c) 2020 Linumiz
|
||||
# Author: Saravanan Sekar <saravanan@linumiz.com>
|
||||
|
||||
zephyr_sources(soc.c)
|
||||
|
||||
zephyr_include_directories(.)
|
||||
|
||||
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
|
||||
14
soc/nuvoton/numicro/m48x/Kconfig
Normal file
14
soc/nuvoton/numicro/m48x/Kconfig
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
# Copyright (c) 2020 Linumiz
|
||||
# Author: Saravanan Sekar <saravanan@linumiz.com>
|
||||
|
||||
config SOC_SERIES_M48X
|
||||
select ARM
|
||||
select CPU_CORTEX_M4
|
||||
select CPU_CORTEX_M_HAS_DWT
|
||||
select CPU_HAS_FPU
|
||||
select CPU_HAS_ARM_MPU
|
||||
|
||||
config SOC_M487
|
||||
select HAS_NUMICRO_HAL
|
||||
10
soc/nuvoton/numicro/m48x/Kconfig.defconfig
Normal file
10
soc/nuvoton/numicro/m48x/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
# Copyright (c) 2020 Linumiz
|
||||
# Author: Saravanan Sekar <saravanan@linumiz.com>
|
||||
|
||||
if SOC_SERIES_M48X
|
||||
|
||||
rsource "Kconfig.defconfig.m48*"
|
||||
|
||||
endif # SOC_SERIES_M48X
|
||||
11
soc/nuvoton/numicro/m48x/Kconfig.defconfig.m487
Normal file
11
soc/nuvoton/numicro/m48x/Kconfig.defconfig.m487
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
# Copyright (c) 2020 Linumiz
|
||||
# Author: Saravanan Sekar <saravanan@linumiz.com>
|
||||
|
||||
if SOC_M487
|
||||
|
||||
config NUM_IRQS
|
||||
default 108
|
||||
|
||||
endif # SOC_M487
|
||||
20
soc/nuvoton/numicro/m48x/Kconfig.soc
Normal file
20
soc/nuvoton/numicro/m48x/Kconfig.soc
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
# Copyright (c) 2020 Linumiz
|
||||
# Author: Saravanan Sekar <saravanan@linumiz.com>
|
||||
|
||||
config SOC_SERIES_M48X
|
||||
bool
|
||||
select SOC_FAMILY_NUMICRO
|
||||
help
|
||||
Enable support for NUVOTON M48X MCU series
|
||||
|
||||
config SOC_M487
|
||||
bool
|
||||
select SOC_SERIES_M48X
|
||||
|
||||
config SOC_SERIES
|
||||
default "m48x" if SOC_SERIES_M48X
|
||||
|
||||
config SOC
|
||||
default "m487" if SOC_M487
|
||||
33
soc/nuvoton/numicro/m48x/soc.c
Normal file
33
soc/nuvoton/numicro/m48x/soc.c
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Copyright (c) 2020 Linumiz
|
||||
* Author: Saravanan Sekar <saravanan@linumiz.com>
|
||||
*/
|
||||
|
||||
#include <zephyr/init.h>
|
||||
#include <zephyr/kernel.h>
|
||||
|
||||
void z_arm_platform_init(void)
|
||||
{
|
||||
SYS_UnlockReg();
|
||||
|
||||
/* system clock init */
|
||||
SystemInit();
|
||||
|
||||
/* Enable HXT clock (external XTAL 12MHz) */
|
||||
CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
|
||||
|
||||
/* Wait for HXT clock ready */
|
||||
CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
|
||||
|
||||
/* Set core clock as PLL_FOUT source */
|
||||
CLK_SetCoreClock(FREQ_192MHZ);
|
||||
|
||||
/* Set both PCLK0 and PCLK1 as HCLK/2 */
|
||||
CLK->PCLKDIV = (CLK_PCLKDIV_APB0DIV_DIV2 | CLK_PCLKDIV_APB1DIV_DIV2);
|
||||
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
SYS_LockReg();
|
||||
}
|
||||
14
soc/nuvoton/numicro/m48x/soc.h
Normal file
14
soc/nuvoton/numicro/m48x/soc.h
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Linumiz
|
||||
* Author: Saravanan Sekar <saravanan@linumiz.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_SOC_ARM_NUVOTON_M48X_SOC_H_
|
||||
#define ZEPHYR_SOC_ARM_NUVOTON_M48X_SOC_H_
|
||||
|
||||
#include <zephyr/sys/util.h>
|
||||
#include <NuMicro.h>
|
||||
|
||||
#endif /* ZEPHYR_SOC_ARM_NUVOTON_M48X_SOC_H_*/
|
||||
6
soc/nuvoton/numicro/soc.yml
Normal file
6
soc/nuvoton/numicro/soc.yml
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
family:
|
||||
- name: numicro
|
||||
series:
|
||||
- name: m48x
|
||||
socs:
|
||||
- name: m487
|
||||
Loading…
Add table
Add a link
Reference in a new issue