gpio: add driver for Intel Apollo Lake SoC
This adds a driver for GPIO controller on the Intel Apollo Lake SoC. Origin: Original Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung
Anas Nashif
parent
eb6ea28649
commit
8d18ebde9b
10 changed files with 866 additions and 0 deletions
469
drivers/gpio/gpio_intel_apl.c
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469
drivers/gpio/gpio_intel_apl.c
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/*
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* Copyright (c) 2018 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Intel Apollo Lake SoC GPIO Controller Driver
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*
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* The GPIO controller on Intel Apollo Lake SoC serves
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* both GPIOs and Pinmuxing function. This driver provides
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* the GPIO function.
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*
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* Currently, this driver does not handle pin triggering.
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*
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* Note that since the GPIO controller controls more then 32 pins,
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* the pin_mux of the API does not work anymore.
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*/
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#include <errno.h>
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#include <gpio.h>
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#include <soc.h>
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#include <sys_io.h>
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#include <misc/slist.h>
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#include "gpio_utils.h"
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#define NUM_ISLANDS 4
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#define REG_PAD_BASE_ADDR 0x000C
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#define REG_MISCCFG 0x0010
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#define MISCCFG_IRQ_ROUTE_POS 3
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#define REG_PAD_OWNER_BASE 0x0020
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#define PAD_OWN_MASK 0x03
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#define PAD_OWN_HOST 0
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#define PAD_OWN_CSME 1
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#define PAD_OWN_ISH 2
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#define PAD_OWN_IE 3
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#define REG_PAD_HOST_SW_OWNER 0x0080
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#define PAD_HOST_SW_OWN_GPIO 1
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#define PAD_HOST_SW_OWN_ACPI 0
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#define REG_GPI_INT_STS_BASE 0x0100
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#define REG_GPI_INT_EN_BASE 0x0110
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#define PAD_CFG0_RXPADSTSEL BIT(29)
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#define PAD_CFG0_RXRAW1 BIT(28)
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#define PAD_CFG0_PMODE_MASK (0x0F << 10)
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#define PAD_CFG0_RXEVCFG_POS 25
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#define PAD_CFG0_RXEVCFG_MASK (0x03 << PAD_CFG0_RXEVCFG_POS)
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#define PAD_CFG0_RXEVCFG_LEVEL (0 << PAD_CFG0_RXEVCFG_POS)
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#define PAD_CFG0_RXEVCFG_EDGE (1 << PAD_CFG0_RXEVCFG_POS)
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#define PAD_CFG0_RXEVCFG_DRIVE0 (2 << PAD_CFG0_RXEVCFG_POS)
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#define PAD_CFG0_PREGFRXSEL BIT(24)
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#define PAD_CFG0_RXINV BIT(23)
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#define PAD_CFG0_RXDIS BIT(9)
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#define PAD_CFG0_TXDIS BIT(8)
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#define PAD_CFG0_RXSTATE BIT(1)
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#define PAD_CFG0_RXSTATE_POS 1
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#define PAD_CFG0_TXSTATE BIT(0)
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#define PAD_CFG0_TXSTATE_POS 0
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#define PAD_CFG1_IOSTERM_POS 8
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#define PAD_CFG1_IOSTERM_MASK (0x03 << PAD_CFG1_IOSTERM_POS)
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#define PAD_CFG1_IOSTERM_FUNC (0 << PAD_CFG1_IOSTERM_POS)
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#define PAD_CFG1_IOSTERM_DISPUD (1 << PAD_CFG1_IOSTERM_POS)
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#define PAD_CFG1_IOSTERM_PU (2 << PAD_CFG1_IOSTERM_POS)
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#define PAD_CFG1_IOSTERM_PD (3 << PAD_CFG1_IOSTERM_POS)
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#define PAD_CFG1_TERM_POS 10
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#define PAD_CFG1_TERM_MASK (0x0F << PAD_CFG1_TERM_POS)
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#define PAD_CFG1_TERM_NONE (0x00 << PAD_CFG1_TERM_POS)
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#define PAD_CFG1_TERM_PD (0x04 << PAD_CFG1_TERM_POS)
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#define PAD_CFG1_TERM_PU (0x0C << PAD_CFG1_TERM_POS)
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#define PAD_CFG1_IOSSTATE_POS 14
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#define PAD_CFG1_IOSSTATE_MASK (0x0F << PAD_CFG1_IOSSTATE_POS)
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#define PAD_CFG1_IOSSTATE_IGNORE (0x0F << PAD_CFG1_IOSSTATE_POS)
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struct apl_gpio_island {
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u32_t reg_base;
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u32_t num_pins;
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};
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struct gpio_intel_apl_config {
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struct apl_gpio_island islands[NUM_ISLANDS];
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};
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struct gpio_intel_apl_data {
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/* Pad base address for each island */
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u32_t pad_base[NUM_ISLANDS];
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sys_slist_t cb;
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};
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static inline void extract_island_and_pin(u32_t pin, u32_t *island,
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u32_t *raw_pin)
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{
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*island = pin >> APL_GPIO_ISLAND_POS;
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*raw_pin = pin & APL_GPIO_PIN_MASK;
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}
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#ifdef CONFIG_GPIO_INTEL_APL_CHECK_PERMS
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/**
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* @brief Check if host has permission to alter this GPIO pin.
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*
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* @param "struct device *dev" Device struct
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* @param "u32_t island" Island index
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* @param "u32_t raw_pin" Raw GPIO pin
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*
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* @return true if host owns the GPIO pin, false otherwise
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*/
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static bool check_perm(struct device *dev, u32_t island, u32_t raw_pin)
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{
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const struct gpio_intel_apl_config *cfg = dev->config->config_info;
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struct gpio_intel_apl_data *data = dev->driver_data;
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u32_t offset, val;
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/* First is to establish that host software owns the pin */
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/* read the Pad Ownership register related to the pin */
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offset = REG_PAD_OWNER_BASE + ((raw_pin >> 3) << 2);
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val = sys_read32(cfg->islands[island].reg_base + offset);
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/* get the bits about ownership */
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offset = raw_pin % 8;
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val = (val >> offset) & PAD_OWN_MASK;
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if (val) {
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/* PAD_OWN_HOST == 0, so !0 => false*/
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return false;
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}
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/* Also need to make sure the function of pad is GPIO */
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offset = data->pad_base[island] + (raw_pin << 3);
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val = sys_read32(cfg->islands[island].reg_base + offset);
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if (val & PAD_CFG0_PMODE_MASK) {
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/* mode is not zero => not functioning as GPIO */
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return false;
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}
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return true;
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}
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#else
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#define check_perm(...) (1)
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#endif
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static void gpio_intel_apl_isr(void *arg)
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{
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struct device *dev = arg;
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const struct gpio_intel_apl_config *cfg = dev->config->config_info;
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struct gpio_intel_apl_data *data = dev->driver_data;
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struct gpio_callback *cb;
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u32_t island, raw_pin, reg;
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SYS_SLIST_FOR_EACH_CONTAINER(&data->cb, cb, node) {
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extract_island_and_pin(cb->pin, &island, &raw_pin);
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reg = cfg->islands[island].reg_base + REG_GPI_INT_STS_BASE;
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if (sys_bitfield_test_and_set_bit(reg, raw_pin)) {
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__ASSERT(cb->handler, "No callback handler!");
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cb->handler(dev, cb, cb->pin);
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}
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}
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}
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static int gpio_intel_apl_config(struct device *dev, int access_op,
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u32_t pin, int flags)
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{
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const struct gpio_intel_apl_config *cfg = dev->config->config_info;
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struct gpio_intel_apl_data *data = dev->driver_data;
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u32_t island, raw_pin, reg, cfg0, cfg1, val;
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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if ((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) {
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return -EINVAL;
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}
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if ((flags & GPIO_POL_MASK) == GPIO_POL_INV) {
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/* hardware cannot invert signal */
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return -EINVAL;
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}
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extract_island_and_pin(pin, &island, &raw_pin);
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if (!check_perm(dev, island, raw_pin)) {
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return -EPERM;
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}
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/* Set GPIO to trigger legacy interrupt */
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if (flags & GPIO_INT) {
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reg = cfg->islands[island].reg_base + REG_PAD_HOST_SW_OWNER;
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sys_bitfield_set_bit(reg, raw_pin);
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}
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/* read in pad configuration register */
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reg = cfg->islands[island].reg_base
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+ data->pad_base[island] + (raw_pin * 8);
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cfg0 = sys_read32(reg);
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cfg1 = sys_read32(reg + 4);
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/* change direction */
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if ((flags & GPIO_DIR_MASK) == GPIO_DIR_OUT) {
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/* pin to output */
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cfg0 &= ~PAD_CFG0_TXDIS;
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cfg0 |= PAD_CFG0_RXDIS;
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} else {
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/* pin to input */
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cfg0 &= ~PAD_CFG0_RXDIS;
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cfg0 |= PAD_CFG0_TXDIS;
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/* don't override RX to 1 */
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cfg0 &= ~PAD_CFG0_RXRAW1;
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}
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/* clear some bits first before interrupt setup */
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cfg0 &= ~(PAD_CFG0_RXPADSTSEL | PAD_CFG0_RXINV
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| PAD_CFG0_RXEVCFG_MASK);
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/* setup interrupt if desired */
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if (flags & GPIO_INT) {
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/* invert signal for interrupt controller */
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if (flags & GPIO_INT_ACTIVE_LOW) {
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cfg0 |= PAD_CFG0_RXINV;
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}
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/* level == 0 / edge == 1*/
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if (flags & GPIO_INT_EDGE) {
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cfg0 |= PAD_CFG0_RXEVCFG_EDGE;
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}
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} else {
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/* set RX conf to drive 0 */
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cfg0 |= PAD_CFG0_RXEVCFG_DRIVE0;
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}
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/* pull-up or pull-down */
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val = flags & GPIO_PUD_MASK;
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cfg1 &= ~PAD_CFG1_TERM_MASK;
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if (val == GPIO_PUD_PULL_UP) {
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cfg1 |= PAD_CFG1_TERM_PU;
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} else if (val == GPIO_PUD_PULL_DOWN) {
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cfg1 |= PAD_CFG1_TERM_PD;
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} else {
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cfg1 |= PAD_CFG1_TERM_NONE;
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}
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/* set IO Standby Termination to function mode */
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cfg1 &= ~PAD_CFG1_IOSTERM_MASK;
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/* IO Standby state to TX,RX enabled */
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cfg1 &= ~PAD_CFG1_IOSSTATE_MASK;
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/* write back pad configuration register after all changes */
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sys_write32(cfg0, reg);
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sys_write32(cfg1, (reg + 4));
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return 0;
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}
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static int gpio_intel_apl_write(struct device *dev, int access_op,
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u32_t pin, u32_t value)
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{
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const struct gpio_intel_apl_config *cfg = dev->config->config_info;
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struct gpio_intel_apl_data *data = dev->driver_data;
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u32_t island, raw_pin, reg, val;
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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extract_island_and_pin(pin, &island, &raw_pin);
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if (!check_perm(dev, island, raw_pin)) {
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return -EPERM;
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}
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reg = cfg->islands[island].reg_base
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+ data->pad_base[island] + (raw_pin * 8);
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val = sys_read32(reg);
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if (value) {
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val |= PAD_CFG0_TXSTATE;
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} else {
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val &= ~PAD_CFG0_TXSTATE;
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}
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sys_write32(val, reg);
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return 0;
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}
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static int gpio_intel_apl_read(struct device *dev, int access_op,
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u32_t pin, u32_t *value)
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{
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const struct gpio_intel_apl_config *cfg = dev->config->config_info;
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struct gpio_intel_apl_data *data = dev->driver_data;
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u32_t island, raw_pin, reg, val;
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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extract_island_and_pin(pin, &island, &raw_pin);
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if (!check_perm(dev, island, raw_pin)) {
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return -EPERM;
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}
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reg = cfg->islands[island].reg_base
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+ data->pad_base[island] + (raw_pin * 8);
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val = sys_read32(reg);
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if (!(val & PAD_CFG0_TXDIS)) {
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/* If TX is not disabled, return TX_STATE */
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*value = val & PAD_CFG0_TXSTATE;
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} else {
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/* else just return RX_STATE */
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*value = val & PAD_CFG0_RXSTATE;
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}
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return 0;
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}
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static int gpio_intel_apl_manage_callback(struct device *dev,
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struct gpio_callback *callback,
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bool set)
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{
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struct gpio_intel_apl_data *data = dev->driver_data;
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_gpio_manage_callback(&data->cb, callback, set);
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return 0;
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}
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static int gpio_intel_apl_enable_callback(struct device *dev,
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int access_op, u32_t pin)
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{
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const struct gpio_intel_apl_config *cfg = dev->config->config_info;
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u32_t island, raw_pin, reg;
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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extract_island_and_pin(pin, &island, &raw_pin);
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if (!check_perm(dev, island, raw_pin)) {
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return -EPERM;
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}
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/* clear (by setting) interrupt status bit */
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reg = cfg->islands[island].reg_base + REG_GPI_INT_STS_BASE;
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sys_bitfield_set_bit(reg, raw_pin);
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/* enable interrupt bit */
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reg = cfg->islands[island].reg_base + REG_GPI_INT_EN_BASE;
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sys_bitfield_set_bit(reg, raw_pin);
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return 0;
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}
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static int gpio_intel_apl_disable_callback(struct device *dev,
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int access_op, u32_t pin)
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{
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const struct gpio_intel_apl_config *cfg = dev->config->config_info;
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u32_t island, raw_pin, reg;
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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extract_island_and_pin(pin, &island, &raw_pin);
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if (!check_perm(dev, island, raw_pin)) {
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return -EPERM;
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}
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/* disable interrupt bit */
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reg = cfg->islands[island].reg_base + REG_GPI_INT_EN_BASE;
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sys_bitfield_clear_bit(reg, raw_pin);
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return 0;
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}
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static const struct gpio_driver_api gpio_intel_apl_api = {
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.config = gpio_intel_apl_config,
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.write = gpio_intel_apl_write,
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.read = gpio_intel_apl_read,
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.manage_callback = gpio_intel_apl_manage_callback,
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.enable_callback = gpio_intel_apl_enable_callback,
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.disable_callback = gpio_intel_apl_disable_callback,
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};
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static void gpio_intel_apl_irq_config(struct device *dev);
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int gpio_intel_apl_init(struct device *dev)
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{
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const struct gpio_intel_apl_config *cfg = dev->config->config_info;
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struct gpio_intel_apl_data *data = dev->driver_data;
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int i;
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gpio_intel_apl_irq_config(dev);
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for (i = 0; i < NUM_ISLANDS; i++) {
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data->pad_base[i] = sys_read32(cfg->islands[i].reg_base
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+ REG_PAD_BASE_ADDR);
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/* Set to route interrupt through IRQ 14 */
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sys_bitfield_clear_bit(data->pad_base[i] + REG_MISCCFG,
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MISCCFG_IRQ_ROUTE_POS);
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}
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dev->driver_api = &gpio_intel_apl_api;
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return 0;
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}
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static const struct gpio_intel_apl_config gpio_intel_apl_cfg = {
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.islands = {
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{
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/* North island */
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.reg_base = INTEL_APL_GPIO_0_BASE_ADDRESS_0,
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.num_pins = 78,
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},
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{
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/* Northwest island */
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.reg_base = INTEL_APL_GPIO_0_BASE_ADDRESS_1,
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.num_pins = 77,
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},
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{
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/* West island */
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.reg_base = INTEL_APL_GPIO_0_BASE_ADDRESS_2,
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.num_pins = 47,
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},
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{
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/* Southwest island */
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.reg_base = INTEL_APL_GPIO_0_BASE_ADDRESS_3,
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.num_pins = 43,
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},
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},
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};
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static struct gpio_intel_apl_data gpio_intel_apl_data;
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DEVICE_AND_API_INIT(gpio_intel_apl, INTEL_APL_GPIO_0_LABEL,
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gpio_intel_apl_init,
|
||||
&gpio_intel_apl_data, &gpio_intel_apl_cfg,
|
||||
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
|
||||
&gpio_intel_apl_api);
|
||||
|
||||
static void gpio_intel_apl_irq_config(struct device *dev)
|
||||
{
|
||||
IRQ_CONNECT(INTEL_APL_GPIO_0_IRQ_0, INTEL_APL_GPIO_0_IRQ_0_PRIORITY,
|
||||
gpio_intel_apl_isr, DEVICE_GET(gpio_intel_apl),
|
||||
INTEL_APL_GPIO_0_IRQ_0_SENSE);
|
||||
|
||||
irq_enable(INTEL_APL_GPIO_0_IRQ_0);
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue