diff --git a/drivers/gpio/CMakeLists.txt b/drivers/gpio/CMakeLists.txt
index a5ee19bd175..94d58b5c0d0 100644
--- a/drivers/gpio/CMakeLists.txt
+++ b/drivers/gpio/CMakeLists.txt
@@ -24,5 +24,6 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_STM32      gpio_stm32.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_SAM0       gpio_sam0.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_SAM        gpio_sam.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_SX1509B    gpio_sx1509b.c)
+zephyr_library_sources_ifdef(CONFIG_GPIO_INTEL_APL  gpio_intel_apl.c)
 
 zephyr_library_sources_ifdef(CONFIG_USERSPACE   gpio_handlers.c)
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 98b6104b4d1..d0e01bc7b4b 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -78,4 +78,6 @@ source "drivers/gpio/Kconfig.sx1509b"
 
 source "drivers/gpio/Kconfig.imx"
 
+source "drivers/gpio/Kconfig.intel"
+
 endif # GPIO
diff --git a/drivers/gpio/Kconfig.intel b/drivers/gpio/Kconfig.intel
new file mode 100644
index 00000000000..2147404745f
--- /dev/null
+++ b/drivers/gpio/Kconfig.intel
@@ -0,0 +1,29 @@
+# Kconfig.dw - Intel SoC GPIO configuration options
+#
+#
+# Copyright (c) 2018 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+menuconfig GPIO_INTEL_APL
+	bool "Intel Apollo Lake SoC GPIO"
+	depends on GPIO
+	select HAS_DTS_GPIO
+	help
+	  Enable driver for Intel Apollo Lake SoC GPIO
+
+if GPIO_INTEL_APL
+
+config GPIO_INTEL_APL_CHECK_PERMS
+	bool "Check permissions before manipulating GPIO"
+	default y
+	help
+	  This option enables the checks to make sure the GPIO
+	  pin can be manipulated. Only if the pin is owned by
+	  the host software and its functioning as GPIO, then
+	  the driver allows manipulating the pin.
+
+	  Say y if unsure.
+
+endif # GPIO_INTEL_APL
\ No newline at end of file
diff --git a/drivers/gpio/gpio_intel_apl.c b/drivers/gpio/gpio_intel_apl.c
new file mode 100644
index 00000000000..2ff1eb66e56
--- /dev/null
+++ b/drivers/gpio/gpio_intel_apl.c
@@ -0,0 +1,469 @@
+/*
+ * Copyright (c) 2018 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Intel Apollo Lake SoC GPIO Controller Driver
+ *
+ * The GPIO controller on Intel Apollo Lake SoC serves
+ * both GPIOs and Pinmuxing function. This driver provides
+ * the GPIO function.
+ *
+ * Currently, this driver does not handle pin triggering.
+ *
+ * Note that since the GPIO controller controls more then 32 pins,
+ * the pin_mux of the API does not work anymore.
+ */
+
+#include <errno.h>
+#include <gpio.h>
+#include <soc.h>
+#include <sys_io.h>
+#include <misc/slist.h>
+
+#include "gpio_utils.h"
+
+#define NUM_ISLANDS 4
+
+#define REG_PAD_BASE_ADDR		0x000C
+
+#define REG_MISCCFG			0x0010
+#define MISCCFG_IRQ_ROUTE_POS		3
+
+#define REG_PAD_OWNER_BASE		0x0020
+#define PAD_OWN_MASK			0x03
+#define PAD_OWN_HOST			0
+#define PAD_OWN_CSME			1
+#define PAD_OWN_ISH			2
+#define PAD_OWN_IE			3
+
+#define REG_PAD_HOST_SW_OWNER		0x0080
+#define PAD_HOST_SW_OWN_GPIO		1
+#define PAD_HOST_SW_OWN_ACPI		0
+
+#define REG_GPI_INT_STS_BASE		0x0100
+#define REG_GPI_INT_EN_BASE		0x0110
+
+#define PAD_CFG0_RXPADSTSEL		BIT(29)
+#define PAD_CFG0_RXRAW1			BIT(28)
+
+#define PAD_CFG0_PMODE_MASK		(0x0F << 10)
+
+#define PAD_CFG0_RXEVCFG_POS		25
+#define PAD_CFG0_RXEVCFG_MASK		(0x03 << PAD_CFG0_RXEVCFG_POS)
+#define PAD_CFG0_RXEVCFG_LEVEL		(0 << PAD_CFG0_RXEVCFG_POS)
+#define PAD_CFG0_RXEVCFG_EDGE		(1 << PAD_CFG0_RXEVCFG_POS)
+#define PAD_CFG0_RXEVCFG_DRIVE0		(2 << PAD_CFG0_RXEVCFG_POS)
+
+#define PAD_CFG0_PREGFRXSEL		BIT(24)
+#define PAD_CFG0_RXINV			BIT(23)
+
+#define PAD_CFG0_RXDIS			BIT(9)
+#define PAD_CFG0_TXDIS			BIT(8)
+#define PAD_CFG0_RXSTATE		BIT(1)
+#define PAD_CFG0_RXSTATE_POS		1
+#define PAD_CFG0_TXSTATE		BIT(0)
+#define PAD_CFG0_TXSTATE_POS		0
+
+#define PAD_CFG1_IOSTERM_POS		8
+#define PAD_CFG1_IOSTERM_MASK		(0x03 << PAD_CFG1_IOSTERM_POS)
+#define PAD_CFG1_IOSTERM_FUNC		(0 << PAD_CFG1_IOSTERM_POS)
+#define PAD_CFG1_IOSTERM_DISPUD		(1 << PAD_CFG1_IOSTERM_POS)
+#define PAD_CFG1_IOSTERM_PU		(2 << PAD_CFG1_IOSTERM_POS)
+#define PAD_CFG1_IOSTERM_PD		(3 << PAD_CFG1_IOSTERM_POS)
+
+#define PAD_CFG1_TERM_POS		10
+#define PAD_CFG1_TERM_MASK		(0x0F << PAD_CFG1_TERM_POS)
+#define PAD_CFG1_TERM_NONE		(0x00 << PAD_CFG1_TERM_POS)
+#define PAD_CFG1_TERM_PD		(0x04 << PAD_CFG1_TERM_POS)
+#define PAD_CFG1_TERM_PU		(0x0C << PAD_CFG1_TERM_POS)
+
+#define PAD_CFG1_IOSSTATE_POS		14
+#define PAD_CFG1_IOSSTATE_MASK		(0x0F << PAD_CFG1_IOSSTATE_POS)
+#define PAD_CFG1_IOSSTATE_IGNORE	(0x0F << PAD_CFG1_IOSSTATE_POS)
+
+struct apl_gpio_island {
+	u32_t reg_base;
+	u32_t num_pins;
+};
+
+struct gpio_intel_apl_config {
+	struct apl_gpio_island islands[NUM_ISLANDS];
+};
+
+struct gpio_intel_apl_data {
+	/* Pad base address for each island */
+	u32_t pad_base[NUM_ISLANDS];
+
+	sys_slist_t cb;
+};
+
+static inline void extract_island_and_pin(u32_t pin, u32_t *island,
+					  u32_t *raw_pin)
+{
+	*island = pin >> APL_GPIO_ISLAND_POS;
+	*raw_pin = pin & APL_GPIO_PIN_MASK;
+}
+
+#ifdef CONFIG_GPIO_INTEL_APL_CHECK_PERMS
+/**
+ * @brief Check if host has permission to alter this GPIO pin.
+ *
+ * @param "struct device *dev" Device struct
+ * @param "u32_t island" Island index
+ * @param "u32_t raw_pin" Raw GPIO pin
+ *
+ * @return true if host owns the GPIO pin, false otherwise
+ */
+static bool check_perm(struct device *dev, u32_t island, u32_t raw_pin)
+{
+	const struct gpio_intel_apl_config *cfg = dev->config->config_info;
+	struct gpio_intel_apl_data *data = dev->driver_data;
+	u32_t offset, val;
+
+	/* First is to establish that host software owns the pin */
+
+	/* read the Pad Ownership register related to the pin */
+	offset = REG_PAD_OWNER_BASE + ((raw_pin >> 3) << 2);
+	val = sys_read32(cfg->islands[island].reg_base + offset);
+
+	/* get the bits about ownership */
+	offset = raw_pin % 8;
+	val = (val >> offset) & PAD_OWN_MASK;
+	if (val) {
+		/* PAD_OWN_HOST == 0, so !0 => false*/
+		return false;
+	}
+
+	/* Also need to make sure the function of pad is GPIO */
+	offset = data->pad_base[island] + (raw_pin << 3);
+	val = sys_read32(cfg->islands[island].reg_base + offset);
+	if (val & PAD_CFG0_PMODE_MASK) {
+		/* mode is not zero => not functioning as GPIO */
+		return false;
+	}
+
+	return true;
+}
+#else
+#define check_perm(...) (1)
+#endif
+
+static void gpio_intel_apl_isr(void *arg)
+{
+	struct device *dev = arg;
+	const struct gpio_intel_apl_config *cfg = dev->config->config_info;
+	struct gpio_intel_apl_data *data = dev->driver_data;
+	struct gpio_callback *cb;
+	u32_t island, raw_pin, reg;
+
+	SYS_SLIST_FOR_EACH_CONTAINER(&data->cb, cb, node) {
+		extract_island_and_pin(cb->pin, &island, &raw_pin);
+
+		reg = cfg->islands[island].reg_base + REG_GPI_INT_STS_BASE;
+
+		if (sys_bitfield_test_and_set_bit(reg, raw_pin)) {
+			__ASSERT(cb->handler, "No callback handler!");
+			cb->handler(dev, cb, cb->pin);
+		}
+	}
+}
+
+static int gpio_intel_apl_config(struct device *dev, int access_op,
+				 u32_t pin, int flags)
+{
+	const struct gpio_intel_apl_config *cfg = dev->config->config_info;
+	struct gpio_intel_apl_data *data = dev->driver_data;
+	u32_t island, raw_pin, reg, cfg0, cfg1, val;
+
+	if (access_op != GPIO_ACCESS_BY_PIN) {
+		return -ENOTSUP;
+	}
+
+	if ((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) {
+		return -EINVAL;
+	}
+
+	if ((flags & GPIO_POL_MASK) == GPIO_POL_INV) {
+		/* hardware cannot invert signal */
+		return -EINVAL;
+	}
+
+	extract_island_and_pin(pin, &island, &raw_pin);
+
+	if (!check_perm(dev, island, raw_pin)) {
+		return -EPERM;
+	}
+
+	/* Set GPIO to trigger legacy interrupt */
+	if (flags & GPIO_INT) {
+		reg = cfg->islands[island].reg_base + REG_PAD_HOST_SW_OWNER;
+		sys_bitfield_set_bit(reg, raw_pin);
+	}
+
+	/* read in pad configuration register */
+	reg = cfg->islands[island].reg_base
+		+ data->pad_base[island] + (raw_pin * 8);
+	cfg0 = sys_read32(reg);
+	cfg1 = sys_read32(reg + 4);
+
+	/* change direction */
+	if ((flags & GPIO_DIR_MASK) == GPIO_DIR_OUT) {
+		/* pin to output */
+		cfg0 &= ~PAD_CFG0_TXDIS;
+		cfg0 |= PAD_CFG0_RXDIS;
+	} else {
+		/* pin to input */
+		cfg0 &= ~PAD_CFG0_RXDIS;
+		cfg0 |= PAD_CFG0_TXDIS;
+
+		/* don't override RX to 1 */
+		cfg0 &= ~PAD_CFG0_RXRAW1;
+	}
+
+	/* clear some bits first before interrupt setup */
+	cfg0 &= ~(PAD_CFG0_RXPADSTSEL | PAD_CFG0_RXINV
+		  | PAD_CFG0_RXEVCFG_MASK);
+
+	/* setup interrupt if desired */
+	if (flags & GPIO_INT) {
+		/* invert signal for interrupt controller */
+		if (flags & GPIO_INT_ACTIVE_LOW) {
+			cfg0 |= PAD_CFG0_RXINV;
+		}
+
+		/* level == 0 / edge == 1*/
+		if (flags & GPIO_INT_EDGE) {
+			cfg0 |= PAD_CFG0_RXEVCFG_EDGE;
+		}
+	} else {
+		/* set RX conf to drive 0 */
+		cfg0 |= PAD_CFG0_RXEVCFG_DRIVE0;
+	}
+
+	/* pull-up or pull-down */
+	val = flags & GPIO_PUD_MASK;
+	cfg1 &= ~PAD_CFG1_TERM_MASK;
+	if (val == GPIO_PUD_PULL_UP) {
+		cfg1 |= PAD_CFG1_TERM_PU;
+	} else if (val == GPIO_PUD_PULL_DOWN) {
+		cfg1 |= PAD_CFG1_TERM_PD;
+	} else {
+		cfg1 |= PAD_CFG1_TERM_NONE;
+	}
+
+	/* set IO Standby Termination to function mode */
+	cfg1 &= ~PAD_CFG1_IOSTERM_MASK;
+
+	/* IO Standby state to TX,RX enabled */
+	cfg1 &= ~PAD_CFG1_IOSSTATE_MASK;
+
+	/* write back pad configuration register after all changes */
+	sys_write32(cfg0, reg);
+	sys_write32(cfg1, (reg + 4));
+
+	return 0;
+}
+
+static int gpio_intel_apl_write(struct device *dev, int access_op,
+				u32_t pin, u32_t value)
+{
+	const struct gpio_intel_apl_config *cfg = dev->config->config_info;
+	struct gpio_intel_apl_data *data = dev->driver_data;
+	u32_t island, raw_pin, reg, val;
+
+	if (access_op != GPIO_ACCESS_BY_PIN) {
+		return -ENOTSUP;
+	}
+
+	extract_island_and_pin(pin, &island, &raw_pin);
+
+	if (!check_perm(dev, island, raw_pin)) {
+		return -EPERM;
+	}
+
+	reg = cfg->islands[island].reg_base
+		+ data->pad_base[island] + (raw_pin * 8);
+	val = sys_read32(reg);
+
+	if (value) {
+		val |= PAD_CFG0_TXSTATE;
+	} else {
+		val &= ~PAD_CFG0_TXSTATE;
+	}
+
+	sys_write32(val, reg);
+
+	return 0;
+}
+
+static int gpio_intel_apl_read(struct device *dev, int access_op,
+			       u32_t pin, u32_t *value)
+{
+	const struct gpio_intel_apl_config *cfg = dev->config->config_info;
+	struct gpio_intel_apl_data *data = dev->driver_data;
+	u32_t island, raw_pin, reg, val;
+
+	if (access_op != GPIO_ACCESS_BY_PIN) {
+		return -ENOTSUP;
+	}
+
+	extract_island_and_pin(pin, &island, &raw_pin);
+
+	if (!check_perm(dev, island, raw_pin)) {
+		return -EPERM;
+	}
+
+	reg = cfg->islands[island].reg_base
+		+ data->pad_base[island] + (raw_pin * 8);
+	val = sys_read32(reg);
+
+	if (!(val & PAD_CFG0_TXDIS)) {
+		/* If TX is not disabled, return TX_STATE */
+		*value = val & PAD_CFG0_TXSTATE;
+	} else {
+		/* else just return RX_STATE */
+		*value = val & PAD_CFG0_RXSTATE;
+	}
+
+	return 0;
+}
+
+static int gpio_intel_apl_manage_callback(struct device *dev,
+					  struct gpio_callback *callback,
+					  bool set)
+{
+	struct gpio_intel_apl_data *data = dev->driver_data;
+
+	_gpio_manage_callback(&data->cb, callback, set);
+
+	return 0;
+}
+
+static int gpio_intel_apl_enable_callback(struct device *dev,
+					  int access_op, u32_t pin)
+{
+	const struct gpio_intel_apl_config *cfg = dev->config->config_info;
+	u32_t island, raw_pin, reg;
+
+	if (access_op != GPIO_ACCESS_BY_PIN) {
+		return -ENOTSUP;
+	}
+
+	extract_island_and_pin(pin, &island, &raw_pin);
+
+	if (!check_perm(dev, island, raw_pin)) {
+		return -EPERM;
+	}
+
+	/* clear (by setting) interrupt status bit */
+	reg = cfg->islands[island].reg_base + REG_GPI_INT_STS_BASE;
+	sys_bitfield_set_bit(reg, raw_pin);
+
+	/* enable interrupt bit */
+	reg = cfg->islands[island].reg_base + REG_GPI_INT_EN_BASE;
+	sys_bitfield_set_bit(reg, raw_pin);
+
+	return 0;
+}
+
+static int gpio_intel_apl_disable_callback(struct device *dev,
+					   int access_op, u32_t pin)
+{
+	const struct gpio_intel_apl_config *cfg = dev->config->config_info;
+	u32_t island, raw_pin, reg;
+
+	if (access_op != GPIO_ACCESS_BY_PIN) {
+		return -ENOTSUP;
+	}
+
+	extract_island_and_pin(pin, &island, &raw_pin);
+
+	if (!check_perm(dev, island, raw_pin)) {
+		return -EPERM;
+	}
+
+	/* disable interrupt bit */
+	reg = cfg->islands[island].reg_base + REG_GPI_INT_EN_BASE;
+	sys_bitfield_clear_bit(reg, raw_pin);
+
+	return 0;
+}
+
+static const struct gpio_driver_api gpio_intel_apl_api = {
+	.config = gpio_intel_apl_config,
+	.write = gpio_intel_apl_write,
+	.read = gpio_intel_apl_read,
+	.manage_callback = gpio_intel_apl_manage_callback,
+	.enable_callback = gpio_intel_apl_enable_callback,
+	.disable_callback = gpio_intel_apl_disable_callback,
+};
+
+static void gpio_intel_apl_irq_config(struct device *dev);
+
+int gpio_intel_apl_init(struct device *dev)
+{
+	const struct gpio_intel_apl_config *cfg = dev->config->config_info;
+	struct gpio_intel_apl_data *data = dev->driver_data;
+	int i;
+
+	gpio_intel_apl_irq_config(dev);
+
+	for (i = 0; i < NUM_ISLANDS; i++) {
+		data->pad_base[i] = sys_read32(cfg->islands[i].reg_base
+					       + REG_PAD_BASE_ADDR);
+
+		/* Set to route interrupt through IRQ 14 */
+		sys_bitfield_clear_bit(data->pad_base[i] + REG_MISCCFG,
+				       MISCCFG_IRQ_ROUTE_POS);
+	}
+
+	dev->driver_api = &gpio_intel_apl_api;
+
+	return 0;
+}
+
+static const struct gpio_intel_apl_config gpio_intel_apl_cfg = {
+	.islands = {
+		{
+			/* North island */
+			.reg_base = INTEL_APL_GPIO_0_BASE_ADDRESS_0,
+			.num_pins = 78,
+		},
+		{
+			/* Northwest island */
+			.reg_base = INTEL_APL_GPIO_0_BASE_ADDRESS_1,
+			.num_pins = 77,
+		},
+		{
+			/* West island */
+			.reg_base = INTEL_APL_GPIO_0_BASE_ADDRESS_2,
+			.num_pins = 47,
+		},
+		{
+			/* Southwest island */
+			.reg_base = INTEL_APL_GPIO_0_BASE_ADDRESS_3,
+			.num_pins = 43,
+		},
+	},
+};
+
+static struct gpio_intel_apl_data gpio_intel_apl_data;
+
+DEVICE_AND_API_INIT(gpio_intel_apl, INTEL_APL_GPIO_0_LABEL,
+		    gpio_intel_apl_init,
+		    &gpio_intel_apl_data, &gpio_intel_apl_cfg,
+		    POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
+		    &gpio_intel_apl_api);
+
+static void gpio_intel_apl_irq_config(struct device *dev)
+{
+	IRQ_CONNECT(INTEL_APL_GPIO_0_IRQ_0, INTEL_APL_GPIO_0_IRQ_0_PRIORITY,
+		    gpio_intel_apl_isr, DEVICE_GET(gpio_intel_apl),
+		    INTEL_APL_GPIO_0_IRQ_0_SENSE);
+
+	irq_enable(INTEL_APL_GPIO_0_IRQ_0);
+}
diff --git a/dts/bindings/gpio/intel,apl-gpio.yaml b/dts/bindings/gpio/intel,apl-gpio.yaml
new file mode 100644
index 00000000000..049dfb48e2a
--- /dev/null
+++ b/dts/bindings/gpio/intel,apl-gpio.yaml
@@ -0,0 +1,45 @@
+#
+# Copyright (c) 2018 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+---
+title: Intel Apollo Lake GPIO controller
+id: intel,apl-gpio
+version: 0.1
+
+description: >
+    This is a representation of the Intel Apollo Lake GPIO node
+
+properties:
+    compatible:
+      type: string
+      category: required
+      description: compatible strings
+      constraint: "intel,apl-gpio"
+      generation: define
+
+    reg:
+      type: int
+      description: mmio register space
+      generation: define
+      category: required
+
+    interrupts:
+      type: array
+      category: required
+      description: required interrupts
+      generation: define
+
+    label:
+      type: string
+      category: required
+      description: Human readable string describing the device (used by Zephyr for API name)
+      generation: define
+
+cell_string: GPIO
+
+"#cells":
+  - pin
+  - flags
+...
diff --git a/dts/x86/apollo_lake.dtsi b/dts/x86/apollo_lake.dtsi
index 078e3b0142a..8d7070cd7f1 100644
--- a/dts/x86/apollo_lake.dtsi
+++ b/dts/x86/apollo_lake.dtsi
@@ -42,5 +42,21 @@
 		#size-cells = <1>;
 		compatible = "simple-bus";
 		ranges;
+
+		gpio: gpio@0 {
+			compatible = "intel,apl-gpio";
+			reg = <0xd0c50000 0x1000>,
+			      <0xd0c40000 0x1000>,
+			      <0xd0c70000 0x1000>,
+			      <0xd0c00000 0x1000>;
+			interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			label = "GPIO_0";
+
+			gpio-controller ;
+			#gpio-cells = <2>;
+
+			status = "disabled";
+		};
 	};
 };
diff --git a/soc/x86/apollo_lake/Kconfig.defconfig b/soc/x86/apollo_lake/Kconfig.defconfig
index 771b0dfc8d2..768dafc8e0a 100644
--- a/soc/x86/apollo_lake/Kconfig.defconfig
+++ b/soc/x86/apollo_lake/Kconfig.defconfig
@@ -72,4 +72,11 @@ endif # UART_NS16550_PORT_3
 
 endif # UART_NS16550
 
+if GPIO
+
+config GPIO_INTEL_APL
+	def_bool y
+
+endif # GPIO
+
 endif # SOC_APOLLO_LAKE
diff --git a/soc/x86/apollo_lake/soc.c b/soc/x86/apollo_lake/soc.c
index e8d8060541e..7c171dfe541 100644
--- a/soc/x86/apollo_lake/soc.c
+++ b/soc/x86/apollo_lake/soc.c
@@ -100,4 +100,20 @@ MMU_BOOT_REGION(CONFIG_I2C_7_BASE_ADDR, 0x1000,
 
 #endif  /* CONFIG_I2C */
 
+/* for GPIO controller */
+#ifdef CONFIG_GPIO_INTEL_APL
+MMU_BOOT_REGION(INTEL_APL_GPIO_0_BASE_ADDRESS_0,
+		INTEL_APL_GPIO_0_SIZE_0,
+		(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
+MMU_BOOT_REGION(INTEL_APL_GPIO_0_BASE_ADDRESS_1,
+		INTEL_APL_GPIO_0_SIZE_1,
+		(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
+MMU_BOOT_REGION(INTEL_APL_GPIO_0_BASE_ADDRESS_2,
+		INTEL_APL_GPIO_0_SIZE_2,
+		(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
+MMU_BOOT_REGION(INTEL_APL_GPIO_0_BASE_ADDRESS_3,
+		INTEL_APL_GPIO_0_SIZE_3,
+		(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
+#endif
+
 #endif  /* CONFIG_X86_MMU */
diff --git a/soc/x86/apollo_lake/soc.h b/soc/x86/apollo_lake/soc.h
index d4264a21c3e..eb815366f66 100644
--- a/soc/x86/apollo_lake/soc.h
+++ b/soc/x86/apollo_lake/soc.h
@@ -23,6 +23,8 @@
 #include <random/rand32.h>
 #endif
 
+#include "soc_gpio.h"
+
 #ifdef CONFIG_PCI
 
 /*
diff --git a/soc/x86/apollo_lake/soc_gpio.h b/soc/x86/apollo_lake/soc_gpio.h
new file mode 100644
index 00000000000..5e016ff1f57
--- /dev/null
+++ b/soc/x86/apollo_lake/soc_gpio.h
@@ -0,0 +1,279 @@
+/*
+ * Copyright (c) 2018, Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief GPIO pins macros for the Apollo Lake SoC
+ *
+ * This header file is used to specify the GPIO pins for
+ * the Apollo Lake SoC.
+ */
+
+#ifndef __SOC_GPIO_H_
+#define __SOC_GPIO_H_
+
+#define APL_GPIO_N			0
+#define APL_GPIO_NW			1
+#define APL_GPIO_W			2
+#define APL_GPIO_SW			3
+
+#define APL_GPIO_ISLAND_POS		16
+#define APL_GPIO_PIN_MASK		0xFFFF
+#define APL_GPIO_N_PREFIX		(APL_GPIO_N  << APL_GPIO_ISLAND_POS)
+#define APL_GPIO_NW_PREFIX		(APL_GPIO_NW << APL_GPIO_ISLAND_POS)
+#define APL_GPIO_W_PREFIX		(APL_GPIO_W  << APL_GPIO_ISLAND_POS)
+#define APL_GPIO_SW_PREFIX		(APL_GPIO_SW << APL_GPIO_ISLAND_POS)
+
+#define APL_GPIO_0			(00 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_1			(01 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_2			(02 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_3			(03 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_4			(04 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_5			(05 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_6			(06 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_7			(07 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_8			(08 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_9			(09 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_10			(10 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_11			(11 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_12			(12 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_13			(13 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_14			(14 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_15			(15 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_16			(16 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_17			(17 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_18			(18 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_19			(19 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_20			(20 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_21			(21 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_22			(22 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_23			(23 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_24			(24 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_25			(25 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_26			(26 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_27			(27 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_28			(28 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_29			(29 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_30			(30 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_31			(31 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_32			(32 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_33			(33 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_34			(34 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_35			(35 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_36			(36 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_37			(37 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_38			(38 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_39			(39 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_40			(40 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_41			(41 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_42			(42 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_43			(43 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_44			(44 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_45			(45 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_46			(46 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_47			(47 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_48			(48 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_49			(49 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_62			(50 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_63			(51 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_64			(52 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_65			(53 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_66			(54 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_67			(55 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_68			(56 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_69			(57 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_70			(58 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_71			(59 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_72			(60 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_73			(61 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_TCK			(62 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_TRST_B			(63 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_TMS			(64 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_TDI			(65 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_CX_PMODE		(66 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_CX_PREQ_B		(67 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_JTAGX			(68 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_CX_PRDY_B		(69 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_TDO			(70 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_CNV_BRI_DT		(71 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_CNV_BRI_RSP		(72 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_CNV_RGI_DT		(73 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_CNV_RGI_RSP		(74 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_SVID0_ALERT_B		(75 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_SVOD0_DATA		(76 | APL_GPIO_N_PREFIX)
+#define APL_GPIO_SVOD0_CLK		(77 | APL_GPIO_N_PREFIX)
+
+#define APL_GPIO_187			(00 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_188			(01 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_189			(02 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_190			(03 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_191			(04 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_192			(05 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_193			(06 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_194			(07 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_195			(08 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_196			(09 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_197			(10 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_198			(11 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_199			(12 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_200			(13 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_201			(14 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_202			(15 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_203			(16 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_204			(17 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_PMC_SPI_FS0		(18 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_PMC_SPI_FS1		(19 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_PMC_SPI_FS2		(20 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_PMC_SPI_RXD		(21 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_PMC_SPI_TXC		(22 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_PMC_SPI_CLK		(23 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_PMIC_PWRGOOD		(24 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_PMIC_RESET_B		(25 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_213			(26 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_214			(27 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_215			(28 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_PMIC_THERMTRIP_B	(29 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_PMIC_STDBY		(30 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_PROCHOT_B		(31 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_PMIC_I2C_SCL		(32 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_PMIC_I2C_SDA		(33 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_74			(34 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_75			(35 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_76			(36 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_77			(37 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_78			(38 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_79			(39 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_80			(40 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_81			(41 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_82			(42 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_83			(43 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_84			(44 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_85			(45 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_86			(46 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_87			(47 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_88			(48 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_89			(49 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_90			(50 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_91			(51 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_92			(52 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_97			(53 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_98			(54 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_99			(55 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_100			(56 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_101			(57 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_102			(58 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_103			(59 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_FST_SPI_CLK_FB		(60 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_104			(61 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_105			(62 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_106			(63 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_109			(64 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_110			(65 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_111			(66 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_112			(67 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_113			(68 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_116			(69 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_117			(70 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_118			(71 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_119			(72 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_120			(73 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_121			(74 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_122			(75 | APL_GPIO_NW_PREFIX)
+#define APL_GPIO_123			(76 | APL_GPIO_NW_PREFIX)
+
+#define APL_GPIO_124			(00 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_125			(01 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_126			(02 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_127			(03 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_128			(04 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_129			(05 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_130			(06 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_131			(07 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_132			(08 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_133			(09 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_134			(10 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_135			(11 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_136			(12 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_137			(13 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_138			(14 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_139			(15 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_146			(16 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_147			(17 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_148			(18 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_149			(19 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_150			(20 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_151			(21 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_152			(22 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_153			(23 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_154			(24 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_155			(25 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_209			(26 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_210			(27 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_211			(28 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_212			(29 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_OSC_CLK_OUT_0		(30 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_OSC_CLK_OUT_1		(31 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_OSC_CLK_OUT_2		(32 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_OSC_CLK_OUT_3		(33 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_OSC_CLK_OUT_4		(34 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_PMU_AC_PRESENT		(35 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_PMU_BATLOW_B		(36 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_PMU_PLTRST_B		(37 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_PMU_PWRBTN_B		(38 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_PMU_RESETBUTTON_B	(39 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_PMU_SLP_S0_B		(40 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_PMU_SLP_S3_B		(41 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_PMU_SLP_S4_B		(42 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_PMU_SUSCLK		(43 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_PMU_WAKE_B		(44 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_SUS_STAT_B		(45 | APL_GPIO_W_PREFIX)
+#define APL_GPIO_SUSPWRDNACK		(46 | APL_GPIO_W_PREFIX)
+
+#define APL_GPIO_205			(00 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_206			(01 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_207			(02 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_208			(03 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_156			(04 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_157			(05 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_158			(06 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_159			(07 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_160			(08 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_161			(09 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_162			(10 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_163			(11 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_164			(12 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_165			(13 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_166			(14 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_167			(15 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_168			(16 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_169			(17 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_170			(18 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_171			(19 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_172			(20 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_179			(21 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_173			(22 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_174			(23 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_175			(24 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_176			(25 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_177			(26 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_178			(27 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_186			(28 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_182			(29 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_183			(30 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_SMB_ALERTB		(31 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_SMB_CLK		(32 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_SMB_DATA		(33 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_LPC_ILB_SERIRQ		(34 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_LPC_CLKOUT0		(35 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_LPC_CLKOUT1		(36 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_LPC_AD0		(37 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_LPC_AD1		(38 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_LPC_AD2		(39 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_LPC_AD3		(40 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_LPC_CLKRUNB		(41 | APL_GPIO_SW_PREFIX)
+#define APL_GPIO_LPC_FRAMEB		(42 | APL_GPIO_SW_PREFIX)
+
+#endif /* __SOC_GPIO_H_ */