soc: arm: use sys_cache* for enabling the caches on same70 and samv71
Use the sys_cache* functions to enable the caches on same70 and samv71. This will ensure that CONFIG_CACHE_MANAGEMENT is considered correctly. Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
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2a2919946f
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4 changed files with 32 additions and 20 deletions
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@ -14,6 +14,7 @@ config SOC_SERIES_SAME70
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select CPU_HAS_ICACHE
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select CPU_HAS_ICACHE
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select CPU_HAS_DCACHE
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select CPU_HAS_DCACHE
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select SOC_FAMILY_SAM
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select SOC_FAMILY_SAM
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select INIT_ARCH_HW_AT_BOOT
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select PLATFORM_SPECIFIC_INIT
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select PLATFORM_SPECIFIC_INIT
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select ASF
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select ASF
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select HAS_SWO
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select HAS_SWO
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@ -14,6 +14,8 @@
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#include <zephyr/kernel.h>
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <zephyr/init.h>
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#include <zephyr/cache.h>
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#include <zephyr/arch/cache.h>
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#include <soc.h>
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#include <soc.h>
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#include <cmsis_core.h>
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#include <cmsis_core.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/logging/log.h>
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@ -226,16 +228,19 @@ static ALWAYS_INLINE void clock_init(void)
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void z_arm_platform_init(void)
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void z_arm_platform_init(void)
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{
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{
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if (IS_ENABLED(CONFIG_CACHE_MANAGEMENT) && IS_ENABLED(CONFIG_ICACHE)) {
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/*
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SCB_EnableICache();
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* DTCM is enabled by default at reset, therefore we have to disable
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} else {
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* it first to get the caches into a state where then the
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SCB_DisableICache();
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* sys_cache*-functions can enable them, if requested by the
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}
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* configuration.
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if (IS_ENABLED(CONFIG_CACHE_MANAGEMENT) && IS_ENABLED(CONFIG_DCACHE)) {
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*/
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SCB_EnableDCache();
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SCB_DisableDCache();
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} else {
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SCB_DisableDCache();
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/*
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}
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* Enable the caches only if configured to do so.
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*/
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sys_cache_instr_enable();
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sys_cache_data_enable();
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/*
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/*
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* Set FWS (Flash Wait State) value before increasing Master Clock
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* Set FWS (Flash Wait State) value before increasing Master Clock
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@ -14,6 +14,7 @@ config SOC_SERIES_SAMV71
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select CPU_HAS_ICACHE
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select CPU_HAS_ICACHE
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select CPU_HAS_DCACHE
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select CPU_HAS_DCACHE
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select SOC_FAMILY_SAM
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select SOC_FAMILY_SAM
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select INIT_ARCH_HW_AT_BOOT
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select PLATFORM_SPECIFIC_INIT
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select PLATFORM_SPECIFIC_INIT
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select ASF
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select ASF
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select HAS_SWO
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select HAS_SWO
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@ -14,6 +14,8 @@
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#include <zephyr/kernel.h>
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <zephyr/init.h>
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#include <zephyr/cache.h>
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#include <zephyr/arch/cache.h>
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#include <soc.h>
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#include <soc.h>
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#include <cmsis_core.h>
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#include <cmsis_core.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/logging/log.h>
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@ -226,16 +228,19 @@ static ALWAYS_INLINE void clock_init(void)
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void z_arm_platform_init(void)
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void z_arm_platform_init(void)
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{
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{
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if (IS_ENABLED(CONFIG_CACHE_MANAGEMENT) && IS_ENABLED(CONFIG_ICACHE)) {
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/*
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SCB_EnableICache();
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* DTCM is enabled by default at reset, therefore we have to disable
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} else {
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* it first to get the caches into a state where then the
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SCB_DisableICache();
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* sys_cache*-functions can enable them, if requested by the
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}
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* configuration.
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if (IS_ENABLED(CONFIG_CACHE_MANAGEMENT) && IS_ENABLED(CONFIG_DCACHE)) {
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*/
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SCB_EnableDCache();
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SCB_DisableDCache();
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} else {
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SCB_DisableDCache();
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/*
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}
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* Enable the caches only if configured to do so.
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*/
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sys_cache_instr_enable();
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sys_cache_data_enable();
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/*
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/*
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* Set FWS (Flash Wait State) value before increasing Master Clock
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* Set FWS (Flash Wait State) value before increasing Master Clock
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