From 8b4516226b90fc6c0f8985cc0f3eedebc48aa48a Mon Sep 17 00:00:00 2001
From: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Date: Mon, 18 Dec 2023 10:53:02 +0100
Subject: [PATCH] soc: arm: use sys_cache* for enabling the caches on same70
 and samv71

Use the sys_cache* functions to enable the caches on same70 and
samv71. This will ensure that CONFIG_CACHE_MANAGEMENT is
considered correctly.

Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
---
 soc/arm/atmel_sam/same70/Kconfig.series |  1 +
 soc/arm/atmel_sam/same70/soc.c          | 25 +++++++++++++++----------
 soc/arm/atmel_sam/samv71/Kconfig.series |  1 +
 soc/arm/atmel_sam/samv71/soc.c          | 25 +++++++++++++++----------
 4 files changed, 32 insertions(+), 20 deletions(-)

diff --git a/soc/arm/atmel_sam/same70/Kconfig.series b/soc/arm/atmel_sam/same70/Kconfig.series
index 66ceeb6ca3e..4e7d6aa396e 100644
--- a/soc/arm/atmel_sam/same70/Kconfig.series
+++ b/soc/arm/atmel_sam/same70/Kconfig.series
@@ -14,6 +14,7 @@ config SOC_SERIES_SAME70
 	select CPU_HAS_ICACHE
 	select CPU_HAS_DCACHE
 	select SOC_FAMILY_SAM
+	select INIT_ARCH_HW_AT_BOOT
 	select PLATFORM_SPECIFIC_INIT
 	select ASF
 	select HAS_SWO
diff --git a/soc/arm/atmel_sam/same70/soc.c b/soc/arm/atmel_sam/same70/soc.c
index 79d7c9fa830..f68e520c724 100644
--- a/soc/arm/atmel_sam/same70/soc.c
+++ b/soc/arm/atmel_sam/same70/soc.c
@@ -14,6 +14,8 @@
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
 #include <zephyr/init.h>
+#include <zephyr/cache.h>
+#include <zephyr/arch/cache.h>
 #include <soc.h>
 #include <cmsis_core.h>
 #include <zephyr/logging/log.h>
@@ -226,16 +228,19 @@ static ALWAYS_INLINE void clock_init(void)
 
 void z_arm_platform_init(void)
 {
-	if (IS_ENABLED(CONFIG_CACHE_MANAGEMENT) && IS_ENABLED(CONFIG_ICACHE)) {
-		SCB_EnableICache();
-	} else {
-		SCB_DisableICache();
-	}
-	if (IS_ENABLED(CONFIG_CACHE_MANAGEMENT) && IS_ENABLED(CONFIG_DCACHE)) {
-		SCB_EnableDCache();
-	} else {
-		SCB_DisableDCache();
-	}
+	/*
+	 * DTCM is enabled by default at reset, therefore we have to disable
+	 * it first to get the caches into a state where then the
+	 * sys_cache*-functions can enable them, if requested by the
+	 * configuration.
+	 */
+	SCB_DisableDCache();
+
+	/*
+	 * Enable the caches only if configured to do so.
+	 */
+	sys_cache_instr_enable();
+	sys_cache_data_enable();
 
 	/*
 	 * Set FWS (Flash Wait State) value before increasing Master Clock
diff --git a/soc/arm/atmel_sam/samv71/Kconfig.series b/soc/arm/atmel_sam/samv71/Kconfig.series
index 543def9d9a2..cadee35acb5 100644
--- a/soc/arm/atmel_sam/samv71/Kconfig.series
+++ b/soc/arm/atmel_sam/samv71/Kconfig.series
@@ -14,6 +14,7 @@ config SOC_SERIES_SAMV71
 	select CPU_HAS_ICACHE
 	select CPU_HAS_DCACHE
 	select SOC_FAMILY_SAM
+	select INIT_ARCH_HW_AT_BOOT
 	select PLATFORM_SPECIFIC_INIT
 	select ASF
 	select HAS_SWO
diff --git a/soc/arm/atmel_sam/samv71/soc.c b/soc/arm/atmel_sam/samv71/soc.c
index 7571ce46dc7..f88a3cb440b 100644
--- a/soc/arm/atmel_sam/samv71/soc.c
+++ b/soc/arm/atmel_sam/samv71/soc.c
@@ -14,6 +14,8 @@
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
 #include <zephyr/init.h>
+#include <zephyr/cache.h>
+#include <zephyr/arch/cache.h>
 #include <soc.h>
 #include <cmsis_core.h>
 #include <zephyr/logging/log.h>
@@ -226,16 +228,19 @@ static ALWAYS_INLINE void clock_init(void)
 
 void z_arm_platform_init(void)
 {
-	if (IS_ENABLED(CONFIG_CACHE_MANAGEMENT) && IS_ENABLED(CONFIG_ICACHE)) {
-		SCB_EnableICache();
-	} else {
-		SCB_DisableICache();
-	}
-	if (IS_ENABLED(CONFIG_CACHE_MANAGEMENT) && IS_ENABLED(CONFIG_DCACHE)) {
-		SCB_EnableDCache();
-	} else {
-		SCB_DisableDCache();
-	}
+	/*
+	 * DTCM is enabled by default at reset, therefore we have to disable
+	 * it first to get the caches into a state where then the
+	 * sys_cache*-functions can enable them, if requested by the
+	 * configuration.
+	 */
+	SCB_DisableDCache();
+
+	/*
+	 * Enable the caches only if configured to do so.
+	 */
+	sys_cache_instr_enable();
+	sys_cache_data_enable();
 
 	/*
 	 * Set FWS (Flash Wait State) value before increasing Master Clock