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soc: xtensa: rework DT_L2_SRAM and DT_L2_SRAM

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Rename DT_L2_SRAM_* to just L2_SRAM_* and set it using new DT macros.
Do something similar for DT_LP_SRAM_* renamed to LP_SRAM_*

Updated the intel_gna driver as it used the DT_L2_SRAM_* defines.

This change also lets us remove dts_fixup.h on intel_s1000 and
intel_apl_adsp SoCs.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2020-04-24 14:32:37 -05:00 • committed by Kumar Gala
commit 8aeb8a3814
8 changed files with 26 additions and 46 deletions
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4
drivers/neural_net/intel_gna.c
View file

@ -130,8 +130,8 @@ static int intel_gna_setup_page_table(void *physical, size_t size,
LOG_DBG("physical %p size %u virtual %p", physical, size, virtual); LOG_DBG("physical %p size %u virtual %p", physical, size, virtual);
if (((phys_addr + size - DT_L2_SRAM_BASE) > DT_L2_SRAM_SIZE) || if (((phys_addr + size - L2_SRAM_BASE) > L2_SRAM_SIZE) ||
(phys_addr < DT_L2_SRAM_BASE)) { (phys_addr < L2_SRAM_BASE)) {
LOG_ERR("model at %p of size %u exceeds L2 SRAM space", LOG_ERR("model at %p of size %u exceeds L2 SRAM space",
physical, size); physical, size);
return -EINVAL; return -EINVAL;

2
drivers/neural_net/intel_gna.h
View file

@ -63,7 +63,7 @@ extern "C" {
#define GNA_LAYER_DESC_ALIGN (128) #define GNA_LAYER_DESC_ALIGN (128)
#define GNA_ADDRESSABLE_MEM_SIZE DT_L2_SRAM_SIZE #define GNA_ADDRESSABLE_MEM_SIZE L2_SRAM_SIZE
#define GNA_NUM_PG_TABLE_INDEX_BITS 10 #define GNA_NUM_PG_TABLE_INDEX_BITS 10
#define GNA_NUM_PG_TABLE_ENTRIES BIT(GNA_NUM_PG_TABLE_INDEX_BITS) #define GNA_NUM_PG_TABLE_ENTRIES BIT(GNA_NUM_PG_TABLE_INDEX_BITS)
#define GNA_PG_SIZE_IN_BITSHIFT 12 #define GNA_PG_SIZE_IN_BITSHIFT 12

15
soc/xtensa/intel_apl_adsp/dts_fixup.h
View file

@ -1,15 +0,0 @@
/*
* Copyright (c) 2019 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/* SoC level DTS fixup file */
#define DT_L2_SRAM_BASE CONFIG_SRAM_BASE_ADDRESS
#define DT_L2_SRAM_SIZE (CONFIG_SRAM_SIZE * 1024)
#define DT_LP_SRAM_BASE DT_REG_ADDR(DT_INST(1, mmio_sram))
#define DT_LP_SRAM_SIZE DT_REG_SIZE(DT_INST(1, mmio_sram))
/* End of SoC Level DTS fixup file */

4
soc/xtensa/intel_apl_adsp/linker.ld
View file

@ -439,7 +439,7 @@ SECTIONS
/* stack */ /* stack */
_end = ALIGN(8); _end = ALIGN(8);
PROVIDE(end = ALIGN(8)); PROVIDE(end = ALIGN(8));
__stack = DT_L2_SRAM_BASE + DT_L2_SRAM_SIZE; __stack = L2_SRAM_BASE + L2_SRAM_SIZE;
/* dma buffers */ /* dma buffers */
.lpbuf (NOLOAD): ALIGN(4) .lpbuf (NOLOAD): ALIGN(4)
{ {
@ -447,7 +447,7 @@ SECTIONS
*(.dma_buffers) *(.dma_buffers)
_dma_buf_end = ABSOLUTE(.); _dma_buf_end = ABSOLUTE(.);
} >LPRAM_REGION } >LPRAM_REGION
_heap_sentry = DT_L2_SRAM_BASE + DT_L2_SRAM_SIZE; _heap_sentry = L2_SRAM_BASE + L2_SRAM_SIZE;
.comment 0 : { *(.comment) } .comment 0 : { *(.comment) }
.debug 0 : { *(.debug) } .debug 0 : { *(.debug) }
.line 0 : { *(.line) } .line 0 : { *(.line) }

15
soc/xtensa/intel_apl_adsp/memory.h
View file

@ -9,12 +9,15 @@
/* L2 HP SRAM */ /* L2 HP SRAM */
#define HP_RAM_RESERVE_HEADER_SPACE 0x00010000 #define HP_RAM_RESERVE_HEADER_SPACE 0x00010000
#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
#ifdef CONFIG_BOOTLOADER_MCUBOOT #ifdef CONFIG_BOOTLOADER_MCUBOOT
#define SRAM_BASE (DT_L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K) #define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
#define SRAM_SIZE (DT_L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K) #define SRAM_SIZE (L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
#else #else
#define SRAM_BASE (DT_L2_SRAM_BASE) #define SRAM_BASE (L2_SRAM_BASE)
#define SRAM_SIZE (DT_L2_SRAM_SIZE) #define SRAM_SIZE (L2_SRAM_SIZE)
#endif #endif
/* The reset vector address in SRAM and its size */ /* The reset vector address in SRAM and its size */
@ -91,8 +94,8 @@
#define IDT_SIZE 0x2000 #define IDT_SIZE 0x2000
/* low power ram where DMA buffers are typically placed */ /* low power ram where DMA buffers are typically placed */
#define LPRAM_BASE (DT_LP_SRAM_BASE) #define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
#define LPRAM_SIZE (DT_LP_SRAM_SIZE) #define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
#include <platform/memory.h> #include <platform/memory.h>

11
soc/xtensa/intel_s1000/dts_fixup.h
View file

@ -1,11 +0,0 @@
/* SPDX-License-Identifier: Apache-2.0 */
/* SoC level DTS fixup file */
#define DT_L2_SRAM_BASE CONFIG_SRAM_BASE_ADDRESS
#define DT_L2_SRAM_SIZE CONFIG_SRAM_SIZE * 1024
#define DT_LP_SRAM_BASE DT_REG_ADDR(DT_INST(1, mmio_sram))
#define DT_LP_SRAM_SIZE DT_REG_SIZE(DT_INST(1, mmio_sram))
/* End of SoC Level DTS fixup file */

4
soc/xtensa/intel_s1000/linker.ld
View file

@ -449,7 +449,7 @@ SECTIONS
/* stack */ /* stack */
_end = ALIGN(8); _end = ALIGN(8);
PROVIDE(end = ALIGN(8)); PROVIDE(end = ALIGN(8));
__stack = DT_L2_SRAM_BASE + DT_L2_SRAM_SIZE; __stack = L2_SRAM_BASE + L2_SRAM_SIZE;
/* dma buffers */ /* dma buffers */
.lpbuf (NOLOAD): ALIGN(4) .lpbuf (NOLOAD): ALIGN(4)
{ {
@ -457,7 +457,7 @@ SECTIONS
*(.dma_buffers) *(.dma_buffers)
_dma_buf_end = ABSOLUTE(.); _dma_buf_end = ABSOLUTE(.);
} >LPRAM_REGION } >LPRAM_REGION
_heap_sentry = DT_L2_SRAM_BASE + DT_L2_SRAM_SIZE; _heap_sentry = L2_SRAM_BASE + L2_SRAM_SIZE;
.comment 0 : { *(.comment) } .comment 0 : { *(.comment) }
.debug 0 : { *(.debug) } .debug 0 : { *(.debug) }
.line 0 : { *(.line) } .line 0 : { *(.line) }

17
soc/xtensa/intel_s1000/memory.h
View file

@ -11,12 +11,15 @@
/* L2 HP SRAM */ /* L2 HP SRAM */
#define L2_VECTOR_SIZE 0x1000 #define L2_VECTOR_SIZE 0x1000
#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
#ifdef CONFIG_BOOTLOADER_MCUBOOT #ifdef CONFIG_BOOTLOADER_MCUBOOT
#define SRAM_BASE (DT_L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K) #define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
#define SRAM_SIZE (DT_L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K) #define SRAM_SIZE (L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
#else #else
#define SRAM_BASE (DT_L2_SRAM_BASE) #define SRAM_BASE (L2_SRAM_BASE)
#define SRAM_SIZE (DT_L2_SRAM_SIZE) #define SRAM_SIZE (L2_SRAM_SIZE)
#endif #endif
/* The reset vector address in SRAM and its size */ /* The reset vector address in SRAM and its size */
@ -66,10 +69,10 @@
#define IDT_SIZE 0x2000 #define IDT_SIZE 0x2000
/* low power ram where DMA buffers are typically placed */ /* low power ram where DMA buffers are typically placed */
#define LPRAM_BASE (DT_LP_SRAM_BASE) #define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
#define LPRAM_SIZE (DT_LP_SRAM_SIZE) #define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
/* Boot vector resideing in LP-SRAM for core #1 */ /* Boot vector resideing in LP-SRAM for core #1 */
#define LPSRAM_BOOT_VECTOR_ADDR (DT_LP_SRAM_BASE + 0x08) #define LPSRAM_BOOT_VECTOR_ADDR (LP_SRAM_BASE + 0x08)
#endif /* __INC_MEMORY_H */ #endif /* __INC_MEMORY_H */