From 8aeb8a381480aa45975c6a7f1d79315e95da1101 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 24 Apr 2020 14:32:37 -0500 Subject: [PATCH] soc: xtensa: rework DT_L2_SRAM and DT_L2_SRAM Rename DT_L2_SRAM_* to just L2_SRAM_* and set it using new DT macros. Do something similar for DT_LP_SRAM_* renamed to LP_SRAM_* Updated the intel_gna driver as it used the DT_L2_SRAM_* defines. This change also lets us remove dts_fixup.h on intel_s1000 and intel_apl_adsp SoCs. Signed-off-by: Kumar Gala --- drivers/neural_net/intel_gna.c | 4 ++-- drivers/neural_net/intel_gna.h | 2 +- soc/xtensa/intel_apl_adsp/dts_fixup.h | 15 --------------- soc/xtensa/intel_apl_adsp/linker.ld | 4 ++-- soc/xtensa/intel_apl_adsp/memory.h | 15 +++++++++------ soc/xtensa/intel_s1000/dts_fixup.h | 11 ----------- soc/xtensa/intel_s1000/linker.ld | 4 ++-- soc/xtensa/intel_s1000/memory.h | 17 ++++++++++------- 8 files changed, 26 insertions(+), 46 deletions(-) delete mode 100644 soc/xtensa/intel_apl_adsp/dts_fixup.h delete mode 100644 soc/xtensa/intel_s1000/dts_fixup.h diff --git a/drivers/neural_net/intel_gna.c b/drivers/neural_net/intel_gna.c index e2b6c9466c4..17019895185 100644 --- a/drivers/neural_net/intel_gna.c +++ b/drivers/neural_net/intel_gna.c @@ -130,8 +130,8 @@ static int intel_gna_setup_page_table(void *physical, size_t size, LOG_DBG("physical %p size %u virtual %p", physical, size, virtual); - if (((phys_addr + size - DT_L2_SRAM_BASE) > DT_L2_SRAM_SIZE) || - (phys_addr < DT_L2_SRAM_BASE)) { + if (((phys_addr + size - L2_SRAM_BASE) > L2_SRAM_SIZE) || + (phys_addr < L2_SRAM_BASE)) { LOG_ERR("model at %p of size %u exceeds L2 SRAM space", physical, size); return -EINVAL; diff --git a/drivers/neural_net/intel_gna.h b/drivers/neural_net/intel_gna.h index 8baec360dbc..95735703e04 100644 --- a/drivers/neural_net/intel_gna.h +++ b/drivers/neural_net/intel_gna.h @@ -63,7 +63,7 @@ extern "C" { #define GNA_LAYER_DESC_ALIGN (128) -#define GNA_ADDRESSABLE_MEM_SIZE DT_L2_SRAM_SIZE +#define GNA_ADDRESSABLE_MEM_SIZE L2_SRAM_SIZE #define GNA_NUM_PG_TABLE_INDEX_BITS 10 #define GNA_NUM_PG_TABLE_ENTRIES BIT(GNA_NUM_PG_TABLE_INDEX_BITS) #define GNA_PG_SIZE_IN_BITSHIFT 12 diff --git a/soc/xtensa/intel_apl_adsp/dts_fixup.h b/soc/xtensa/intel_apl_adsp/dts_fixup.h deleted file mode 100644 index 6a457f58887..00000000000 --- a/soc/xtensa/intel_apl_adsp/dts_fixup.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2019 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* SoC level DTS fixup file */ - -#define DT_L2_SRAM_BASE CONFIG_SRAM_BASE_ADDRESS -#define DT_L2_SRAM_SIZE (CONFIG_SRAM_SIZE * 1024) - -#define DT_LP_SRAM_BASE DT_REG_ADDR(DT_INST(1, mmio_sram)) -#define DT_LP_SRAM_SIZE DT_REG_SIZE(DT_INST(1, mmio_sram)) - -/* End of SoC Level DTS fixup file */ diff --git a/soc/xtensa/intel_apl_adsp/linker.ld b/soc/xtensa/intel_apl_adsp/linker.ld index bbc6d4e94d8..31d64e821db 100644 --- a/soc/xtensa/intel_apl_adsp/linker.ld +++ b/soc/xtensa/intel_apl_adsp/linker.ld @@ -439,7 +439,7 @@ SECTIONS /* stack */ _end = ALIGN(8); PROVIDE(end = ALIGN(8)); - __stack = DT_L2_SRAM_BASE + DT_L2_SRAM_SIZE; + __stack = L2_SRAM_BASE + L2_SRAM_SIZE; /* dma buffers */ .lpbuf (NOLOAD): ALIGN(4) { @@ -447,7 +447,7 @@ SECTIONS *(.dma_buffers) _dma_buf_end = ABSOLUTE(.); } >LPRAM_REGION - _heap_sentry = DT_L2_SRAM_BASE + DT_L2_SRAM_SIZE; + _heap_sentry = L2_SRAM_BASE + L2_SRAM_SIZE; .comment 0 : { *(.comment) } .debug 0 : { *(.debug) } .line 0 : { *(.line) } diff --git a/soc/xtensa/intel_apl_adsp/memory.h b/soc/xtensa/intel_apl_adsp/memory.h index 4e57e493df7..2d526bd0560 100644 --- a/soc/xtensa/intel_apl_adsp/memory.h +++ b/soc/xtensa/intel_apl_adsp/memory.h @@ -9,12 +9,15 @@ /* L2 HP SRAM */ #define HP_RAM_RESERVE_HEADER_SPACE 0x00010000 +#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0))) +#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0))) + #ifdef CONFIG_BOOTLOADER_MCUBOOT -#define SRAM_BASE (DT_L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K) -#define SRAM_SIZE (DT_L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K) +#define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K) +#define SRAM_SIZE (L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K) #else -#define SRAM_BASE (DT_L2_SRAM_BASE) -#define SRAM_SIZE (DT_L2_SRAM_SIZE) +#define SRAM_BASE (L2_SRAM_BASE) +#define SRAM_SIZE (L2_SRAM_SIZE) #endif /* The reset vector address in SRAM and its size */ @@ -91,8 +94,8 @@ #define IDT_SIZE 0x2000 /* low power ram where DMA buffers are typically placed */ -#define LPRAM_BASE (DT_LP_SRAM_BASE) -#define LPRAM_SIZE (DT_LP_SRAM_SIZE) +#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) +#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1))) #include diff --git a/soc/xtensa/intel_s1000/dts_fixup.h b/soc/xtensa/intel_s1000/dts_fixup.h deleted file mode 100644 index 998d1f5d5a7..00000000000 --- a/soc/xtensa/intel_s1000/dts_fixup.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -/* SoC level DTS fixup file */ - -#define DT_L2_SRAM_BASE CONFIG_SRAM_BASE_ADDRESS -#define DT_L2_SRAM_SIZE CONFIG_SRAM_SIZE * 1024 - -#define DT_LP_SRAM_BASE DT_REG_ADDR(DT_INST(1, mmio_sram)) -#define DT_LP_SRAM_SIZE DT_REG_SIZE(DT_INST(1, mmio_sram)) - -/* End of SoC Level DTS fixup file */ diff --git a/soc/xtensa/intel_s1000/linker.ld b/soc/xtensa/intel_s1000/linker.ld index 671a2e2e869..ecf5669f65b 100644 --- a/soc/xtensa/intel_s1000/linker.ld +++ b/soc/xtensa/intel_s1000/linker.ld @@ -449,7 +449,7 @@ SECTIONS /* stack */ _end = ALIGN(8); PROVIDE(end = ALIGN(8)); - __stack = DT_L2_SRAM_BASE + DT_L2_SRAM_SIZE; + __stack = L2_SRAM_BASE + L2_SRAM_SIZE; /* dma buffers */ .lpbuf (NOLOAD): ALIGN(4) { @@ -457,7 +457,7 @@ SECTIONS *(.dma_buffers) _dma_buf_end = ABSOLUTE(.); } >LPRAM_REGION - _heap_sentry = DT_L2_SRAM_BASE + DT_L2_SRAM_SIZE; + _heap_sentry = L2_SRAM_BASE + L2_SRAM_SIZE; .comment 0 : { *(.comment) } .debug 0 : { *(.debug) } .line 0 : { *(.line) } diff --git a/soc/xtensa/intel_s1000/memory.h b/soc/xtensa/intel_s1000/memory.h index 53e9639bda6..6e7f42e7d6d 100644 --- a/soc/xtensa/intel_s1000/memory.h +++ b/soc/xtensa/intel_s1000/memory.h @@ -11,12 +11,15 @@ /* L2 HP SRAM */ #define L2_VECTOR_SIZE 0x1000 +#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0))) +#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0))) + #ifdef CONFIG_BOOTLOADER_MCUBOOT -#define SRAM_BASE (DT_L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K) -#define SRAM_SIZE (DT_L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K) +#define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K) +#define SRAM_SIZE (L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K) #else -#define SRAM_BASE (DT_L2_SRAM_BASE) -#define SRAM_SIZE (DT_L2_SRAM_SIZE) +#define SRAM_BASE (L2_SRAM_BASE) +#define SRAM_SIZE (L2_SRAM_SIZE) #endif /* The reset vector address in SRAM and its size */ @@ -66,10 +69,10 @@ #define IDT_SIZE 0x2000 /* low power ram where DMA buffers are typically placed */ -#define LPRAM_BASE (DT_LP_SRAM_BASE) -#define LPRAM_SIZE (DT_LP_SRAM_SIZE) +#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) +#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1))) /* Boot vector resideing in LP-SRAM for core #1 */ -#define LPSRAM_BOOT_VECTOR_ADDR (DT_LP_SRAM_BASE + 0x08) +#define LPSRAM_BOOT_VECTOR_ADDR (LP_SRAM_BASE + 0x08) #endif /* __INC_MEMORY_H */