From 8ae0bb8b703c66a2d4118a04573b5f5f1058a261 Mon Sep 17 00:00:00 2001 From: Mulin Chao Date: Tue, 2 May 2023 02:28:18 -0700 Subject: [PATCH] soc: npcx: add soc drivers for npcx4 series This CL adds the soc drivers for npcx4 series. Besides adding npcx4m3f and npcx4m8f support, we also modified the register offset of LV_GPIO_CTL and PUPD_EN for npcx4 series. Signed-off-by: Mulin Chao --- soc/arm/nuvoton_npcx/Kconfig | 2 ++ soc/arm/nuvoton_npcx/common/ecst/ecst.py | 6 ++--- soc/arm/nuvoton_npcx/common/ecst/ecst_args.py | 2 ++ soc/arm/nuvoton_npcx/common/reg/reg_def.h | 18 +++++++++++---- soc/arm/nuvoton_npcx/common/soc_clock.h | 9 +++++--- soc/arm/nuvoton_npcx/npcx4/CMakeLists.txt | 7 ++++++ .../npcx4/Kconfig.defconfig.npcx4m3f | 11 +++++++++ .../npcx4/Kconfig.defconfig.npcx4m8f | 11 +++++++++ .../npcx4/Kconfig.defconfig.series | 23 +++++++++++++++++++ soc/arm/nuvoton_npcx/npcx4/Kconfig.series | 15 ++++++++++++ soc/arm/nuvoton_npcx/npcx4/Kconfig.soc | 16 +++++++++++++ soc/arm/nuvoton_npcx/npcx4/linker.ld | 9 ++++++++ soc/arm/nuvoton_npcx/npcx4/soc.c | 21 +++++++++++++++++ soc/arm/nuvoton_npcx/npcx4/soc.h | 22 ++++++++++++++++++ 14 files changed, 161 insertions(+), 11 deletions(-) create mode 100644 soc/arm/nuvoton_npcx/npcx4/CMakeLists.txt create mode 100644 soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.npcx4m3f create mode 100644 soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.npcx4m8f create mode 100644 soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.series create mode 100644 soc/arm/nuvoton_npcx/npcx4/Kconfig.series create mode 100644 soc/arm/nuvoton_npcx/npcx4/Kconfig.soc create mode 100644 soc/arm/nuvoton_npcx/npcx4/linker.ld create mode 100644 soc/arm/nuvoton_npcx/npcx4/soc.c create mode 100644 soc/arm/nuvoton_npcx/npcx4/soc.h diff --git a/soc/arm/nuvoton_npcx/Kconfig b/soc/arm/nuvoton_npcx/Kconfig index ac5daf8e0b7..27b260025cc 100644 --- a/soc/arm/nuvoton_npcx/Kconfig +++ b/soc/arm/nuvoton_npcx/Kconfig @@ -42,6 +42,8 @@ config NPCX_HEADER_CHIP default "npcx9m3" if SOC_NPCX9M3F default "npcx9m6" if SOC_NPCX9M6F default "npcx9m7" if SOC_NPCX9M7F + default "npcx4m3" if SOC_NPCX4M3F + default "npcx4m8" if SOC_NPCX4M8F choice NPCX_HEADER_SPI_MAX_CLOCK_CHOICE prompt "Clock rate to use for SPI flash" diff --git a/soc/arm/nuvoton_npcx/common/ecst/ecst.py b/soc/arm/nuvoton_npcx/common/ecst/ecst.py index 33c2fe1c401..1e05f479c2c 100755 --- a/soc/arm/nuvoton_npcx/common/ecst/ecst.py +++ b/soc/arm/nuvoton_npcx/common/ecst/ecst.py @@ -213,8 +213,8 @@ def _check_chip(output, ecst_args): if ecst_args.chip_name == INVALID_INPUT: message = f'Invalid chip name, ' - message += "should be npcx9m8, npcx9m7, npcx9m6, npcx7m7," \ - " npcx7m6, npcx7m5, npcx5m5 or npcx5m6." + message += "should be npcx4m3, npcx4m8, npcx9m8, npcx9m7, npcx9m6, " \ + "npcx7m7, npcx7m6, npcx7m5." _exit_with_failure_delete_file(output, message) def _set_anchor(output, ecst_args): @@ -924,7 +924,7 @@ def _crc_update(cur, crc, table): :param crc :param table """ - l_crc = (0x000000ff & cur) + l_crc = 0x000000ff & cur tmp = crc ^ l_crc crc = (crc >> 8) ^ table[(tmp & 0xff)] diff --git a/soc/arm/nuvoton_npcx/common/ecst/ecst_args.py b/soc/arm/nuvoton_npcx/common/ecst/ecst_args.py index cf129bb324d..e580758f274 100755 --- a/soc/arm/nuvoton_npcx/common/ecst/ecst_args.py +++ b/soc/arm/nuvoton_npcx/common/ecst/ecst_args.py @@ -53,6 +53,8 @@ CHIPS_INFO = { 'npcx9m3': {'ram_address': 0x10080000, 'ram_size': 0x50000}, 'npcx9m6': {'ram_address': 0x10090000, 'ram_size': 0x40000}, 'npcx9m7': {'ram_address': 0x10070000, 'ram_size': 0x60000}, + 'npcx4m3': {'ram_address': 0x10088000, 'ram_size': 0x50000}, + 'npcx4m8': {'ram_address': 0x10060000, 'ram_size': 0x7c800}, } DEFAULT_CHIP = 'npcx7m6' diff --git a/soc/arm/nuvoton_npcx/common/reg/reg_def.h b/soc/arm/nuvoton_npcx/common/reg/reg_def.h index 283f9bd200a..098550c5cca 100644 --- a/soc/arm/nuvoton_npcx/common/reg/reg_def.h +++ b/soc/arm/nuvoton_npcx/common/reg/reg_def.h @@ -241,15 +241,23 @@ static inline uint32_t npcx_devalt_lk_offset(uint32_t alt_lk_no) static inline uint32_t npcx_pupd_en_offset(uint32_t pupd_en_no) { - return 0x28 + pupd_en_no; + if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7) || IS_ENABLED(CONFIG_SOC_SERIES_NPCX9)) { + return 0x28 + pupd_en_no; + } else { /* NPCX4 and later series */ + return 0x2b + pupd_en_no; + } } static inline uint32_t npcx_lv_gpio_ctl_offset(uint32_t ctl_no) { - if (ctl_no < 5) { - return 0x02a + ctl_no; - } else { - return 0x026 + ctl_no - 5; + if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7) || IS_ENABLED(CONFIG_SOC_SERIES_NPCX9)) { + if (ctl_no < 5) { + return 0x02a + ctl_no; + } else { + return 0x026 + ctl_no - 5; + } + } else { /* NPCX4 and later series */ + return 0x150 + ctl_no; } } diff --git a/soc/arm/nuvoton_npcx/common/soc_clock.h b/soc/arm/nuvoton_npcx/common/soc_clock.h index 99656d38c8a..afefba88e4b 100644 --- a/soc/arm/nuvoton_npcx/common/soc_clock.h +++ b/soc/arm/nuvoton_npcx/common/soc_clock.h @@ -44,11 +44,11 @@ struct npcx_clk_cfg { #define APB3DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb3_prescaler) - 1) /* APB4 clock divider if supported */ #if DT_NODE_HAS_PROP(DT_NODELABEL(pcc), apb4_prescaler) -#if defined(CONFIG_SOC_SERIES_NPCX9) +#if !defined(CONFIG_SOC_SERIES_NPCX7) /* Supported in NPCX9 and later series */ #define APB4DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb4_prescaler) - 1) #else #error "APB4 clock divider is not supported but defined in pcc node!" -#endif +#endif /* !CONFIG_SOC_SERIES_NPCX7 */ #endif /* @@ -101,7 +101,10 @@ struct npcx_clk_cfg { #else #define HFCGN_VAL 0x02 #endif -#if (OFMCLK == 100000000) +#if (OFMCLK == 120000000) +#define HFCGMH_VAL 0x0E +#define HFCGML_VAL 0x4E +#elif (OFMCLK == 100000000) #define HFCGMH_VAL 0x0B #define HFCGML_VAL 0xEC #elif (OFMCLK == 96000000) diff --git a/soc/arm/nuvoton_npcx/npcx4/CMakeLists.txt b/soc/arm/nuvoton_npcx/npcx4/CMakeLists.txt new file mode 100644 index 00000000000..ee55c1c2a5b --- /dev/null +++ b/soc/arm/nuvoton_npcx/npcx4/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) + +zephyr_sources( + soc.c +) diff --git a/soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.npcx4m3f b/soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.npcx4m3f new file mode 100644 index 00000000000..d56b4fac925 --- /dev/null +++ b/soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.npcx4m3f @@ -0,0 +1,11 @@ +# Nuvoton Cortex-M4 Embedded Controller + +# Copyright (c) 2023 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_NPCX4M3F + +config SOC + default "npcx4m3f" + +endif # SOC_NPCX4M3F diff --git a/soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.npcx4m8f b/soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.npcx4m8f new file mode 100644 index 00000000000..00ba5b3b623 --- /dev/null +++ b/soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.npcx4m8f @@ -0,0 +1,11 @@ +# Nuvoton Cortex-M4 Embedded Controller + +# Copyright (c) 2023 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_NPCX4M8F + +config SOC + default "npcx4m8f" + +endif # SOC_NPCX4M8F diff --git a/soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.series b/soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.series new file mode 100644 index 00000000000..018a38cc14b --- /dev/null +++ b/soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.series @@ -0,0 +1,23 @@ +# Nuvoton Cortex-M4 Embedded Controller + +# Copyright (c) 2023 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_NPCX4 + +config SOC_SERIES + default "npcx4" + +config NUM_IRQS + default 128 + +config CORTEX_M_SYSTICK + default !NPCX_ITIM_TIMER + +config ESPI_NPCX + default y + depends on ESPI + +source "soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.npcx4*" + +endif # SOC_SERIES_NPCX4 diff --git a/soc/arm/nuvoton_npcx/npcx4/Kconfig.series b/soc/arm/nuvoton_npcx/npcx4/Kconfig.series new file mode 100644 index 00000000000..2eb4ac5d184 --- /dev/null +++ b/soc/arm/nuvoton_npcx/npcx4/Kconfig.series @@ -0,0 +1,15 @@ +# Nuvoton Cortex-M4 Embedded Controller NPCX4 series + +# Copyright (c) 2023 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NPCX4 + bool "Nuvoton NPCX4 Series" + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select SOC_FAMILY_NPCX + help + Enable support for Nuvoton NPCX4 series diff --git a/soc/arm/nuvoton_npcx/npcx4/Kconfig.soc b/soc/arm/nuvoton_npcx/npcx4/Kconfig.soc new file mode 100644 index 00000000000..3e5f5e1d195 --- /dev/null +++ b/soc/arm/nuvoton_npcx/npcx4/Kconfig.soc @@ -0,0 +1,16 @@ +# Nuvoton NPCX4 EC series + +# Copyright (c) 2023 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +choice + prompt "NPCX4 Selection" + depends on SOC_SERIES_NPCX4 + +config SOC_NPCX4M3F + bool "NPCX4M3F" + +config SOC_NPCX4M8F + bool "NPCX4M8F" + +endchoice diff --git a/soc/arm/nuvoton_npcx/npcx4/linker.ld b/soc/arm/nuvoton_npcx/npcx4/linker.ld new file mode 100644 index 00000000000..7b1a0772918 --- /dev/null +++ b/soc/arm/nuvoton_npcx/npcx4/linker.ld @@ -0,0 +1,9 @@ +/* linker.ld - Linker command/script file */ + +/* + * Copyright (c) 2023 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/soc/arm/nuvoton_npcx/npcx4/soc.c b/soc/arm/nuvoton_npcx/npcx4/soc.c new file mode 100644 index 00000000000..29c0976adfa --- /dev/null +++ b/soc/arm/nuvoton_npcx/npcx4/soc.c @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2023 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); + +static int soc_init(void) +{ + + return 0; +} + +SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); diff --git a/soc/arm/nuvoton_npcx/npcx4/soc.h b/soc/arm/nuvoton_npcx/npcx4/soc.h new file mode 100644 index 00000000000..e61c1e108f0 --- /dev/null +++ b/soc/arm/nuvoton_npcx/npcx4/soc.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2023 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _NUVOTON_NPCX_SOC_H_ +#define _NUVOTON_NPCX_SOC_H_ + +/* CMSIS required definitions */ +#define __FPU_PRESENT CONFIG_CPU_HAS_FPU +#define __MPU_PRESENT CONFIG_CPU_HAS_ARM_MPU + + +#include +#include +#include +#include +#include +#include + +#endif /* _NUVOTON_NPCX_SOC_H_ */