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riscv: add support for thread local storage

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Adds the necessary bits to initialize TLS in the stack
area and sets up CPU registers during context switch.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung 2020-10-02 13:09:32 -07:00 • committed by Andrew Boie
commit 8a79ce1428
6 changed files with 44 additions and 0 deletions
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soc/riscv/openisa_rv32m1/linker.ld
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@ -122,6 +122,7 @@ SECTIONS
_image_rodata_start = .;
#include <linker/common-rom.ld>
#include <linker/thread-local-storage.ld>
SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
{