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riscv: add support for thread local storage

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Adds the necessary bits to initialize TLS in the stack
area and sets up CPU registers during context switch.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung 2020-10-02 13:09:32 -07:00 • committed by Andrew Boie
commit 8a79ce1428
6 changed files with 44 additions and 0 deletions
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5
arch/riscv/core/thread.c
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@ -30,6 +30,11 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
stack_init->a1 = (ulong_t)p1;
stack_init->a2 = (ulong_t)p2;
stack_init->a3 = (ulong_t)p3;
#ifdef CONFIG_THREAD_LOCAL_STORAGE
stack_init->tp = (ulong_t)thread->tls;
#endif
/*
* Following the RISC-V architecture,
* the MSTATUS register (used to globally enable/disable interrupt),