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soc: arm: atmel_sam: sam3x: Rework clock_init

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Update clock_init for the Atmel SAM3X SoC using the new PMC API.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
This commit is contained in:
Pieter De Gendt 2023-12-20 11:59:06 +01:00 • committed by Fabio Baltieri
commit 89f23f7947
1 changed files with 65 additions and 161 deletions
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226
soc/arm/atmel_sam/sam3x/soc.c
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@ -2,6 +2,7 @@
* Copyright (c) 2013-2015 Wind River Systems, Inc. * Copyright (c) 2013-2015 Wind River Systems, Inc.
* Copyright (c) 2016 Intel Corporation. * Copyright (c) 2016 Intel Corporation.
* Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com> * Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com>
* Copyright (c) 2023 Basalte bv
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -14,25 +15,9 @@
* for the Atmel SAM3X series processor. * for the Atmel SAM3X series processor.
*/ */
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h> #include <soc.h>
#include <soc_pmc.h>
/* #include <soc_supc.h>
* PLL clock = Main * (MULA + 1) / DIVA
*
* By default, MULA == 6, DIVA == 1.
* With main crystal running at 12 MHz,
* PLL = 12 * (6 + 1) / 1 = 84 MHz
*
* With Processor Clock prescaler at 1
* Processor Clock (HCLK) = 84 MHz.
*/
#define PMC_CKGR_PLLAR_MULA \
(CKGR_PLLAR_MULA(CONFIG_SOC_ATMEL_SAM3X_PLLA_MULA))
#define PMC_CKGR_PLLAR_DIVA \
(CKGR_PLLAR_DIVA(CONFIG_SOC_ATMEL_SAM3X_PLLA_DIVA))
/** /**
* @brief Setup various clocks on SoC at boot time. * @brief Setup various clocks on SoC at boot time.
@ -42,158 +27,34 @@
*/ */
static ALWAYS_INLINE void clock_init(void) static ALWAYS_INLINE void clock_init(void)
{ {
uint32_t reg_val; /* Switch the main clock to the internal OSC with 12MHz */
soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ);
#ifdef CONFIG_SOC_ATMEL_SAM3X_EXT_SLCK /* Switch MCK (Master Clock) to the main clock */
/* Switch slow clock to the external 32 kHz crystal oscillator */ soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK);
SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL;
/* Wait for oscillator to be stabilized */ EFC0->EEFC_FMR = EEFC_FMR_FWS(0);
while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL)) { EFC1->EEFC_FMR = EEFC_FMR_FWS(0);
;
}
#endif /* CONFIG_SOC_ATMEL_SAM3X_EXT_SLCK */
#ifdef CONFIG_SOC_ATMEL_SAM3X_EXT_MAINCK soc_pmc_enable_clock_failure_detector();
/*
* Setup main external crystal oscillator
*/
/* Start the external crystal oscillator */ if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM3X_EXT_SLCK)) {
PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD soc_supc_slow_clock_select_crystal_osc();
/* Fast RC Oscillator Frequency is at 4 MHz (default) */
| CKGR_MOR_MOSCRCF_4_MHz
/* We select maximum setup time. While start up time
* could be shortened this optimization is not deemed
* critical now.
*/
| CKGR_MOR_MOSCXTST(0xFFu)
/* RC OSC must stay on */
| CKGR_MOR_MOSCRCEN
| CKGR_MOR_MOSCXTEN;
/* Wait for oscillator to be stabilized */
while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
;
} }
/* Select the external crystal oscillator as the main clock source */ if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM3X_EXT_MAINCK)) {
PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD /*
| CKGR_MOR_MOSCRCF_4_MHz * Setup main external crystal oscillator.
| CKGR_MOR_MOSCSEL */
| CKGR_MOR_MOSCXTST(0xFFu)
| CKGR_MOR_MOSCRCEN
| CKGR_MOR_MOSCXTEN;
/* Wait for external oscillator to be selected */ /* We select maximum setup time.
while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) { * While start up time could be shortened
; * this optimization is not deemed
* critical now.
*/
soc_pmc_switch_mainck_to_xtal(false, 0xff);
} }
/* Turn off RC OSC, not used any longer, to save power */
PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
| CKGR_MOR_MOSCSEL
| CKGR_MOR_MOSCXTST(0xFFu)
| CKGR_MOR_MOSCXTEN;
/* Wait for RC OSC to be turned off */
while (PMC->PMC_SR & PMC_SR_MOSCRCS) {
;
}
#ifdef CONFIG_SOC_ATMEL_SAM3X_WAIT_MODE
/*
* Instruct CPU to enter Wait mode instead of Sleep mode to
* keep Processor Clock (HCLK) and thus be able to debug
* CPU using JTAG
*/
PMC->PMC_FSMR |= PMC_FSMR_LPM;
#endif
#else
/*
* Setup main fast RC oscillator
*/
/*
* NOTE: MOSCRCF must be changed only if MOSCRCS is set in the PMC_SR
* register, should normally be the case here
*/
while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) {
;
}
/* Set main fast RC oscillator to 12 MHz */
PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
| CKGR_MOR_MOSCRCF_12_MHz
| CKGR_MOR_MOSCRCEN;
/* Wait for oscillator to be stabilized */
while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) {
;
}
#endif /* CONFIG_SOC_ATMEL_SAM3X_EXT_MAINCK */
/*
* Setup PLLA
*/
/* Switch MCK (Master Clock) to the main clock first */
reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk;
PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_MAIN_CLK;
/* Wait for clock selection to complete */
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
;
}
/* Setup PLLA */
PMC->CKGR_PLLAR = CKGR_PLLAR_ONE
| PMC_CKGR_PLLAR_MULA
| CKGR_PLLAR_PLLACOUNT(0x3Fu)
| PMC_CKGR_PLLAR_DIVA;
/*
* NOTE: Both MULA and DIVA must be set to a value greater than 0 or
* otherwise PLL will be disabled. In this case we would get stuck in
* the following loop.
*/
/* Wait for PLL lock */
while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {
;
}
/*
* Final setup of the Master Clock
*/
/*
* NOTE: PMC_MCKR must not be programmed in a single write operation.
* If CSS or PRES are modified we must wait for MCKRDY bit to be
* set again.
*/
/* Setup prescaler - PLLA Clock / Processor Clock (HCLK) */
reg_val = PMC->PMC_MCKR & ~PMC_MCKR_PRES_Msk;
PMC->PMC_MCKR = reg_val | PMC_MCKR_PRES_CLK_1;
/* Wait for Master Clock setup to complete */
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
;
}
/* Finally select PLL as Master Clock source */
reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk;
PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_PLLA_CLK;
/* Wait for Master Clock setup to complete */
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
;
}
}
void z_arm_platform_init(void)
{
/* /*
* Set FWS (Flash Wait State) value before increasing Master Clock * Set FWS (Flash Wait State) value before increasing Master Clock
* (MCK) frequency. * (MCK) frequency.
@ -203,6 +64,49 @@ void z_arm_platform_init(void)
EFC0->EEFC_FMR = EEFC_FMR_FWS(4); EFC0->EEFC_FMR = EEFC_FMR_FWS(4);
EFC1->EEFC_FMR = EEFC_FMR_FWS(4); EFC1->EEFC_FMR = EEFC_FMR_FWS(4);
/*
* Setup PLLA
*/
/*
* PLL clock = Main * (MULA + 1) / DIVA
*
* By default, MULA == 6, DIVA == 1.
* With main crystal running at 12 MHz,
* PLL = 12 * (6 + 1) / 1 = 84 MHz
*
* With Processor Clock prescaler at 1
* Processor Clock (HCLK) = 84 MHz.
*/
soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM3X_PLLA_MULA, 0x3Fu,
CONFIG_SOC_ATMEL_SAM3X_PLLA_DIVA);
/*
* Final setup of the Master Clock
*/
/* prescaler has to be set before PLL lock */
soc_pmc_mck_set_prescaler(1);
/* Select PLL as Master Clock source. */
soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK);
/* Disable internal fast RC if we have an external crystal oscillator */
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM3X_EXT_MAINCK)) {
soc_pmc_osc_disable_fastrc();
}
}
void z_arm_platform_init(void)
{
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM3X_WAIT_MODE)) {
/*
* Instruct CPU to enter Wait mode instead of Sleep mode to
* keep Processor Clock (HCLK) and thus be able to debug
* CPU using JTAG.
*/
soc_pmc_enable_waitmode();
}
/* Setup system clocks */ /* Setup system clocks */
clock_init(); clock_init();
} }