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soc: riscv: sifive-freedom: fix SYS_CLOCK_HW_CYCLES_PER_SEC value

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This commit fixes the default value of SYS_CLOCK_HW_CYCLES_PER_SEC
option. The previous value of 32768 is not consistent with the
documentation of FE310 SoC. Only FE310-based boards rely on the default
value of this option; other boards from the Freedom series define it
themselves.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit is contained in:
Filip Kokosinski 2022-03-23 13:39:41 +01:00 • committed by Carles Cufí
commit 8388bb7c24
1 changed files with 1 additions and 1 deletions
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soc/riscv/riscv-privilege/sifive-freedom/Kconfig.defconfig.series
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@ -6,7 +6,7 @@ config SOC_SERIES
default "sifive-freedom"
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 32768
default 320000
config RISCV_SOC_INTERRUPT_INIT
default y