From 8388bb7c24bca94a5d40dba0a36e79b80647be6b Mon Sep 17 00:00:00 2001 From: Filip Kokosinski Date: Wed, 23 Mar 2022 13:39:41 +0100 Subject: [PATCH] soc: riscv: sifive-freedom: fix SYS_CLOCK_HW_CYCLES_PER_SEC value This commit fixes the default value of SYS_CLOCK_HW_CYCLES_PER_SEC option. The previous value of 32768 is not consistent with the documentation of FE310 SoC. Only FE310-based boards rely on the default value of this option; other boards from the Freedom series define it themselves. Signed-off-by: Filip Kokosinski --- .../riscv-privilege/sifive-freedom/Kconfig.defconfig.series | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/soc/riscv/riscv-privilege/sifive-freedom/Kconfig.defconfig.series b/soc/riscv/riscv-privilege/sifive-freedom/Kconfig.defconfig.series index 0c3cd541773..59c47394ad4 100644 --- a/soc/riscv/riscv-privilege/sifive-freedom/Kconfig.defconfig.series +++ b/soc/riscv/riscv-privilege/sifive-freedom/Kconfig.defconfig.series @@ -6,7 +6,7 @@ config SOC_SERIES default "sifive-freedom" config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 + default 320000 config RISCV_SOC_INTERRUPT_INIT default y