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ARC: cleanup instruction cache initialization

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As of today during the Zephyr start we
 - invalidate I$
 - disable I$
 - enable I$

Given that we don't need to have I$ disabled during any
initialization period and ARC processors have caches enabled
after reset the I$ disabling/enabling is excessive, so we can
drop it.

By that we also aligh the I$ initialization on ARC with other
projects like U-boot and Linux kernel.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
This commit is contained in:
Eugeniy Paltsev 2021-02-25 00:56:32 +03:00 • committed by Anas Nashif
commit 8165f3ad80
5 changed files with 7 additions and 72 deletions
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1
arch/arc/core/arc_smp.c
View file

@ -72,7 +72,6 @@ void z_arc_slave_start(int cpu_num)
arch_cpustart_t fn; arch_cpustart_t fn;
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
z_icache_setup();
z_irq_setup(); z_irq_setup();
z_arc_connect_ici_clear(); z_arc_connect_ici_clear();

1
arch/arc/core/prep_c.c
View file

@ -85,7 +85,6 @@ extern FUNC_NORETURN void z_cstart(void);
void _PrepC(void) void _PrepC(void)
{ {
z_icache_setup();
z_bss_zero(); z_bss_zero();
z_data_copy(); z_data_copy();
z_cstart(); z_cstart();

17
arch/arc/core/reset.S
View file

@ -95,13 +95,10 @@ SECTION_FUNC(TEXT,__start)
kflag r0 kflag r0
#endif #endif
mov_s r1, 1 /* Invalidate icache */
invalidate_and_disable_icache:
lr r0, [_ARC_V2_I_CACHE_BUILD] lr r0, [_ARC_V2_I_CACHE_BUILD]
and.f r0, r0, 0xff and.f r0, r0, 0xff
bz.nd invalidate_dcache bz.nd done_icache_invalidate
mov_s r2, 0 mov_s r2, 0
sr r2, [_ARC_V2_IC_IVIC] sr r2, [_ARC_V2_IC_IVIC]
@ -109,17 +106,17 @@ invalidate_and_disable_icache:
nop_s nop_s
nop_s nop_s
nop_s nop_s
sr r1, [_ARC_V2_IC_CTRL] done_icache_invalidate:
invalidate_dcache:
/* Invalidate dcache */
lr r3, [_ARC_V2_D_CACHE_BUILD] lr r3, [_ARC_V2_D_CACHE_BUILD]
and.f r3, r3, 0xff and.f r3, r3, 0xff
bz.nd done_cache_invalidate bz.nd done_dcache_invalidate
mov_s r1, 1
sr r1, [_ARC_V2_DC_IVDC] sr r1, [_ARC_V2_DC_IVDC]
done_cache_invalidate: done_dcache_invalidate:
/* /*
* Init ARC internal architecture state * Init ARC internal architecture state

1
arch/arc/include/kernel_arch_func.h
View file

@ -25,7 +25,6 @@
#include <kernel_arch_data.h> #include <kernel_arch_data.h>
#ifdef CONFIG_CPU_ARCV2 #ifdef CONFIG_CPU_ARCV2
#include <v2/cache.h>
#include <v2/irq.h> #include <v2/irq.h>
#endif #endif

59
arch/arc/include/v2/cache.h
View file

@ -1,59 +0,0 @@
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Cache helper functions and defines (ARC)
*
* This file contains cache related functions and definitions for the
* ARCv2 processor architecture.
*/
#ifndef ZEPHYR_ARCH_ARC_INCLUDE_V2_CACHE_H_
#define ZEPHYR_ARCH_ARC_INCLUDE_V2_CACHE_H_
#include <arch/cpu.h>
#ifndef _ASMLANGUAGE
#ifdef __cplusplus
extern "C" {
#endif
/* i-cache defines for IC_CTRL register */
#define IC_CACHE_ENABLE 0x00
#define IC_CACHE_DISABLE 0x01
#define IC_CACHE_DIRECT 0x00
#define IC_CACHE_INDIRECT 0x20
/*
* @brief Initialize the I-cache
*
* Enables the i-cache and sets it to direct access mode.
*/
static ALWAYS_INLINE void z_icache_setup(void)
{
uint32_t icache_config = (
IC_CACHE_DIRECT | /* direct mapping (one-way assoc.) */
IC_CACHE_ENABLE /* i-cache enabled */
);
uint32_t val;
val = z_arc_v2_aux_reg_read(_ARC_V2_I_CACHE_BUILD);
val &= 0xff;
if (val != 0U) { /* is i-cache present? */
/* configure i-cache */
z_arc_v2_aux_reg_write(_ARC_V2_IC_CTRL, icache_config);
}
}
#ifdef __cplusplus
}
#endif
#endif /* _ASMLANGUAGE */
#endif /* ZEPHYR_ARCH_ARC_INCLUDE_V2_CACHE_H_ */