ARC: cleanup instruction cache initialization
As of today during the Zephyr start we - invalidate I$ - disable I$ - enable I$ Given that we don't need to have I$ disabled during any initialization period and ARC processors have caches enabled after reset the I$ disabling/enabling is excessive, so we can drop it. By that we also aligh the I$ initialization on ARC with other projects like U-boot and Linux kernel. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
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5 changed files with 7 additions and 72 deletions
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@ -72,7 +72,6 @@ void z_arc_slave_start(int cpu_num)
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arch_cpustart_t fn;
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#ifdef CONFIG_SMP
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z_icache_setup();
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z_irq_setup();
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z_arc_connect_ici_clear();
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@ -85,7 +85,6 @@ extern FUNC_NORETURN void z_cstart(void);
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void _PrepC(void)
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{
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z_icache_setup();
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z_bss_zero();
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z_data_copy();
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z_cstart();
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@ -95,13 +95,10 @@ SECTION_FUNC(TEXT,__start)
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kflag r0
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#endif
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mov_s r1, 1
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invalidate_and_disable_icache:
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/* Invalidate icache */
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lr r0, [_ARC_V2_I_CACHE_BUILD]
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and.f r0, r0, 0xff
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bz.nd invalidate_dcache
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bz.nd done_icache_invalidate
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mov_s r2, 0
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sr r2, [_ARC_V2_IC_IVIC]
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@ -109,17 +106,17 @@ invalidate_and_disable_icache:
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nop_s
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nop_s
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nop_s
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sr r1, [_ARC_V2_IC_CTRL]
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invalidate_dcache:
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done_icache_invalidate:
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/* Invalidate dcache */
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lr r3, [_ARC_V2_D_CACHE_BUILD]
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and.f r3, r3, 0xff
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bz.nd done_cache_invalidate
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bz.nd done_dcache_invalidate
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mov_s r1, 1
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sr r1, [_ARC_V2_DC_IVDC]
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done_cache_invalidate:
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done_dcache_invalidate:
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/*
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* Init ARC internal architecture state
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@ -25,7 +25,6 @@
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#include <kernel_arch_data.h>
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#ifdef CONFIG_CPU_ARCV2
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#include <v2/cache.h>
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#include <v2/irq.h>
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#endif
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@ -1,59 +0,0 @@
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/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Cache helper functions and defines (ARC)
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*
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* This file contains cache related functions and definitions for the
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* ARCv2 processor architecture.
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*/
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#ifndef ZEPHYR_ARCH_ARC_INCLUDE_V2_CACHE_H_
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#define ZEPHYR_ARCH_ARC_INCLUDE_V2_CACHE_H_
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#include <arch/cpu.h>
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#ifndef _ASMLANGUAGE
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* i-cache defines for IC_CTRL register */
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#define IC_CACHE_ENABLE 0x00
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#define IC_CACHE_DISABLE 0x01
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#define IC_CACHE_DIRECT 0x00
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#define IC_CACHE_INDIRECT 0x20
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/*
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* @brief Initialize the I-cache
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*
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* Enables the i-cache and sets it to direct access mode.
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*/
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static ALWAYS_INLINE void z_icache_setup(void)
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{
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uint32_t icache_config = (
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IC_CACHE_DIRECT | /* direct mapping (one-way assoc.) */
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IC_CACHE_ENABLE /* i-cache enabled */
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);
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uint32_t val;
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val = z_arc_v2_aux_reg_read(_ARC_V2_I_CACHE_BUILD);
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val &= 0xff;
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if (val != 0U) { /* is i-cache present? */
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/* configure i-cache */
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z_arc_v2_aux_reg_write(_ARC_V2_IC_CTRL, icache_config);
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}
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_ARCH_ARC_INCLUDE_V2_CACHE_H_ */
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