drivers: memc: Introduce i.MX RT FlexSPI HyperRAM driver
Add the FlexSPI HyperBUS driver to support HyperRAM external devices. Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
This commit is contained in:
Pieter De Gendt
Maureen Helm
parent
acca3c126c
commit
7f46a59a42
6 changed files with 214 additions and 0 deletions
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@ -5,3 +5,4 @@ zephyr_sources_ifdef(CONFIG_MEMC_STM32_SDRAM memc_stm32_sdram.c)
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zephyr_linker_sources_ifdef(CONFIG_MEMC_STM32_SDRAM SECTIONS memc_stm32_sdram.ld)
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zephyr_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI memc_mcux_flexspi.c)
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zephyr_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI_HYPERRAM memc_mcux_flexspi_hyperram.c)
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@ -4,6 +4,10 @@
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if HAS_MCUX_FLEXSPI
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config MEMC_MCUX_FLEXSPI_HYPERRAM
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bool "MCUX FlexSPI HyperRAM driver"
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select MEMC_MCUX_FLEXSPI
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config MEMC_MCUX_FLEXSPI
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bool
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@ -21,6 +21,7 @@ struct memc_flexspi_config {
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bool ahb_prefetch;
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bool ahb_read_addr_opt;
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bool combination_mode;
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bool sck_differential_clock;
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flexspi_read_sample_clock_t rx_sample_clock;
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};
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@ -113,6 +114,7 @@ static int memc_flexspi_init(const struct device *dev)
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flexspi_config.ahbConfig.enableAHBPrefetch = config->ahb_prefetch;
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flexspi_config.ahbConfig.enableReadAddressOpt = config->ahb_read_addr_opt;
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flexspi_config.enableCombination = config->combination_mode;
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flexspi_config.enableSckBDiffOpt = config->sck_differential_clock;
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flexspi_config.rxSampleClock = config->rx_sample_clock;
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FLEXSPI_Init(config->base, &flexspi_config);
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@ -130,6 +132,7 @@ static int memc_flexspi_init(const struct device *dev)
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.ahb_prefetch = DT_INST_PROP(n, ahb_prefetch), \
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.ahb_read_addr_opt = DT_INST_PROP(n, ahb_read_addr_opt),\
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.combination_mode = DT_INST_PROP(n, combination_mode), \
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.sck_differential_clock = DT_INST_PROP(n, sck_differential_clock), \
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.rx_sample_clock = DT_INST_PROP(n, rx_clock_source), \
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}; \
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\
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191
drivers/memc/memc_mcux_flexspi_hyperram.c
Normal file
191
drivers/memc/memc_mcux_flexspi_hyperram.c
Normal file
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@ -0,0 +1,191 @@
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/*
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* Copyright 2021 Basalte bv
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_imx_flexspi_hyperram
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#include <logging/log.h>
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#include <sys/util.h>
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#include "memc_mcux_flexspi.h"
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LOG_MODULE_DECLARE(memc_flexspi, CONFIG_MEMC_LOG_LEVEL);
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enum {
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READ_DATA,
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WRITE_DATA,
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READ_REG,
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WRITE_REG,
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};
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struct memc_flexspi_hyperram_config {
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char *controller_label;
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flexspi_port_t port;
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flexspi_device_config_t config;
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};
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struct memc_flexspi_hyperram_data {
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const struct device *controller;
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};
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static const uint32_t memc_flexspi_hyperram_lut[][4] = {
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/* Read Data */
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[READ_DATA] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0,
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kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10,
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kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x06),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
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},
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/* Write Data */
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[WRITE_DATA] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20,
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kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10,
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kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x06),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x04,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
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},
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/* Read Register */
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[READ_REG] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xE0,
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kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10,
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kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x06),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
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},
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/* Write Register */
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[WRITE_REG] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x60,
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kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10,
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kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x06),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x04,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
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},
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};
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static int memc_flexspi_hyperram_get_vendor_id(const struct device *dev,
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uint16_t *vendor_id)
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{
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const struct memc_flexspi_hyperram_config *config = dev->config;
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struct memc_flexspi_hyperram_data *data = dev->data;
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uint32_t buffer = 0;
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int ret;
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flexspi_transfer_t transfer = {
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.deviceAddress = 0,
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.port = config->port,
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.cmdType = kFLEXSPI_Read,
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.SeqNumber = 1,
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.seqIndex = READ_REG,
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.data = &buffer,
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.dataSize = 4,
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};
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LOG_DBG("Reading id");
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ret = memc_flexspi_transfer(data->controller, &transfer);
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*vendor_id = buffer & 0xffff;
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return ret;
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}
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static int memc_flexspi_hyperram_init(const struct device *dev)
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{
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const struct memc_flexspi_hyperram_config *config = dev->config;
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struct memc_flexspi_hyperram_data *data = dev->data;
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uint16_t vendor_id;
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data->controller = device_get_binding(config->controller_label);
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if (data->controller == NULL) {
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LOG_ERR("Could not find controller");
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return -EINVAL;
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}
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if (memc_flexspi_set_device_config(data->controller, &config->config,
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config->port)) {
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LOG_ERR("Could not set device configuration");
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return -EINVAL;
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}
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if (memc_flexspi_update_lut(data->controller, 0,
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(const uint32_t *) memc_flexspi_hyperram_lut,
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sizeof(memc_flexspi_hyperram_lut) / 4)) {
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LOG_ERR("Could not update lut");
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return -EINVAL;
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}
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memc_flexspi_reset(data->controller);
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if (memc_flexspi_hyperram_get_vendor_id(dev, &vendor_id)) {
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LOG_ERR("Could not read vendor id");
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return -EIO;
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}
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LOG_DBG("Vendor id: 0x%0x", vendor_id);
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return 0;
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}
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#define CONCAT3(x, y, z) x ## y ## z
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#define CS_INTERVAL_UNIT(unit) \
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CONCAT3(kFLEXSPI_CsIntervalUnit, unit, SckCycle)
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#define AHB_WRITE_WAIT_UNIT(unit) \
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CONCAT3(kFLEXSPI_AhbWriteWaitUnit, unit, AhbCycle)
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#define MEMC_FLEXSPI_DEVICE_CONFIG(n) \
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{ \
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.flexspiRootClk = MHZ(332), \
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.isSck2Enabled = false, \
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.flashSize = DT_INST_PROP(n, size) / 8 / KB(1), \
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.CSIntervalUnit = \
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CS_INTERVAL_UNIT( \
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DT_INST_PROP(n, cs_interval_unit)), \
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.CSInterval = DT_INST_PROP(n, cs_interval), \
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.CSHoldTime = DT_INST_PROP(n, cs_hold_time), \
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.CSSetupTime = DT_INST_PROP(n, cs_setup_time), \
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.dataValidTime = DT_INST_PROP(n, data_valid_time), \
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.columnspace = DT_INST_PROP(n, column_space), \
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.enableWordAddress = DT_INST_PROP(n, word_addressable), \
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.AWRSeqIndex = WRITE_DATA, \
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.AWRSeqNumber = 1, \
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.ARDSeqIndex = READ_DATA, \
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.ARDSeqNumber = 1, \
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.AHBWriteWaitUnit = \
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AHB_WRITE_WAIT_UNIT( \
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DT_INST_PROP(n, ahb_write_wait_unit)), \
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.AHBWriteWaitInterval = \
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DT_INST_PROP(n, ahb_write_wait_interval), \
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.enableWriteMask = true, \
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} \
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#define MEMC_FLEXSPI_HYPERRAM(n) \
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static const struct memc_flexspi_hyperram_config \
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memc_flexspi_hyperram_config_##n = { \
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.controller_label = DT_INST_BUS_LABEL(n), \
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.port = DT_INST_REG_ADDR(n), \
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.config = MEMC_FLEXSPI_DEVICE_CONFIG(n), \
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}; \
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\
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static struct memc_flexspi_hyperram_data \
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memc_flexspi_hyperram_data_##n; \
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\
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DEVICE_DT_INST_DEFINE(n, \
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memc_flexspi_hyperram_init, \
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device_pm_control_nop, \
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&memc_flexspi_hyperram_data_##n, \
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&memc_flexspi_hyperram_config_##n, \
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POST_KERNEL, \
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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NULL);
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DT_INST_FOREACH_STATUS_OKAY(MEMC_FLEXSPI_HYPERRAM)
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8
dts/bindings/mtd/nxp,imx-flexspi-hyperram.yaml
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8
dts/bindings/mtd/nxp,imx-flexspi-hyperram.yaml
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@ -0,0 +1,8 @@
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# Copyright 2021 Basalte bv
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# SPDX-License-Identifier: Apache-2.0
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description: NXP FlexSPI HyperRAM
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compatible: "nxp,imx-flexspi-hyperram"
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include: nxp,imx-flexspi-device.yaml
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@ -48,6 +48,13 @@ properties:
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Combine port A and port B data pins to support octal mode access by
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setting register field MCR0[COMBINATIONEN].
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sck-differential-clock:
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type: boolean
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required: false
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description: |
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Enable/disable SCKB pad use as SCKA differential clock output,
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when enabled, Port B flash access is not available.
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rx-clock-source:
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type: int
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required: false
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