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drivers: adc: add pinctrl driver support

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Replace soc-specific pin functions with Zephyr pinctrl api functions for
pin-mux configuration in npcx adc driver. Please notice users need to
configure the corresponding pinctrl nodes in 'pinctrl-0' property in the
adc0 DT node. For example, if ADC0 and ADC2 channels are selected for
the application, please add the follwoings in your board DT layout file.

&adc0 {
	status = "okay";
	/* Use adc0 channel 0 and 2 for 'adc_api' driver tests */
	pinctrl-0 = <&adc0_chan0_gp45
		     &adc0_chan2_gp43>;
	pinctrl-names = "default";
};

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This commit is contained in:
Mulin Chao 2022-02-21 21:32:10 -08:00 • committed by Maureen Helm
commit 7ef371b2e7
6 changed files with 34 additions and 44 deletions
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5
boards/arm/npcx7m6fb_evb/npcx7m6fb_evb.dts
View file

@ -82,8 +82,11 @@
}; };
&adc0 { &adc0 {
/* ADC pinmux is changed only if related channel is configured. */
status = "okay"; status = "okay";
/* Use adc0 channel 0 and 2 for 'adc_api' driver tests */
pinctrl-0 = <&adc0_chan0_gp45
&adc0_chan2_gp43>;
pinctrl-names = "default";
}; };
&espi0 { &espi0 {

5
boards/arm/npcx9m6f_evb/npcx9m6f_evb.dts
View file

@ -95,8 +95,11 @@
}; };
&adc0 { &adc0 {
/* ADC pinmux is changed only if related channel is configured. */
status = "okay"; status = "okay";
/* Use adc0 channel 0 and 2 for 'adc_api' driver tests */
pinctrl-0 = <&adc0_chan0_gp45
&adc0_chan2_gp43>;
pinctrl-names = "default";
}; };
&espi0 { &espi0 {

30
drivers/adc/adc_npcx.c
View file

@ -10,6 +10,7 @@
#include <zephyr/drivers/adc.h> #include <zephyr/drivers/adc.h>
#include <zephyr/drivers/adc/adc_npcx_threshold.h> #include <zephyr/drivers/adc/adc_npcx_threshold.h>
#include <zephyr/drivers/clock_control.h> #include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/kernel.h> #include <zephyr/kernel.h>
#include <soc.h> #include <soc.h>
@ -26,7 +27,7 @@ LOG_MODULE_REGISTER(adc_npcx, CONFIG_ADC_LOG_LEVEL);
#define ADC_REGULAR_MEAST_VAL 0x0001 #define ADC_REGULAR_MEAST_VAL 0x0001
/* ADC channel number */ /* ADC channel number */
#define NPCX_ADC_CH_COUNT DT_INST_NUM_PINCTRLS_BY_IDX(0, 0) #define NPCX_ADC_CH_COUNT DT_INST_PROP(0, channel_count)
/* ADC targeted operating frequency (2MHz) */ /* ADC targeted operating frequency (2MHz) */
#define NPCX_ADC_CLK 2000000 #define NPCX_ADC_CLK 2000000
@ -49,12 +50,11 @@ struct adc_npcx_config {
uintptr_t base; uintptr_t base;
/* clock configuration */ /* clock configuration */
struct npcx_clk_cfg clk_cfg; struct npcx_clk_cfg clk_cfg;
/* pinmux configuration */
const struct npcx_alt *alts_list;
/* amount of thresholds supported */ /* amount of thresholds supported */
const uint8_t threshold_count; const uint8_t threshold_count;
/* threshold control register offset */ /* threshold control register offset */
const uint16_t threshold_reg_offset; const uint16_t threshold_reg_offset;
const struct pinctrl_dev_config *pcfg;
}; };
struct adc_npcx_threshold_control { struct adc_npcx_threshold_control {
@ -328,7 +328,6 @@ static void adc_context_update_buffer_pointer(struct adc_context *ctx,
static int adc_npcx_channel_setup(const struct device *dev, static int adc_npcx_channel_setup(const struct device *dev,
const struct adc_channel_cfg *channel_cfg) const struct adc_channel_cfg *channel_cfg)
{ {
const struct adc_npcx_config *const config = dev->config;
uint8_t channel_id = channel_cfg->channel_id; uint8_t channel_id = channel_cfg->channel_id;
if (channel_id >= NPCX_ADC_CH_COUNT) { if (channel_id >= NPCX_ADC_CH_COUNT) {
@ -356,13 +355,7 @@ static int adc_npcx_channel_setup(const struct device *dev,
return -ENOTSUP; return -ENOTSUP;
} }
/* Configure pin-mux for ADC channel */ LOG_DBG("ADC channel %d configured", channel_cfg->channel_id);
npcx_pinctrl_mux_configure(config->alts_list + channel_cfg->channel_id,
1, 1);
LOG_DBG("ADC channel %d, alts(%d,%d)", channel_cfg->channel_id,
config->alts_list[channel_cfg->channel_id].group,
config->alts_list[channel_cfg->channel_id].bit);
return 0; return 0;
} }
@ -679,14 +672,16 @@ static const struct adc_driver_api adc_npcx_driver_api = {
static int adc_npcx_init(const struct device *dev); static int adc_npcx_init(const struct device *dev);
static const struct npcx_alt adc_alts[] = NPCX_DT_ALT_ITEMS_LIST(0); PINCTRL_DT_INST_DEFINE(0);
BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
"only one 'nuvoton_npcx_adc' compatible node may be present");
static const struct adc_npcx_config adc_npcx_cfg_0 = { static const struct adc_npcx_config adc_npcx_cfg_0 = {
.base = DT_INST_REG_ADDR(0), .base = DT_INST_REG_ADDR(0),
.clk_cfg = NPCX_DT_CLK_CFG_ITEM(0), .clk_cfg = NPCX_DT_CLK_CFG_ITEM(0),
.alts_list = adc_alts,
.threshold_count = DT_INST_PROP(0, threshold_count), .threshold_count = DT_INST_PROP(0, threshold_count),
.threshold_reg_offset = DT_INST_PROP(0, threshold_reg_offset), .threshold_reg_offset = DT_INST_PROP(0, threshold_reg_offset),
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
}; };
static struct adc_npcx_threshold_data threshold_data_0; static struct adc_npcx_threshold_data threshold_data_0;
@ -758,7 +753,12 @@ static int adc_npcx_init(const struct device *dev)
/* Initialize mutex of ADC channels */ /* Initialize mutex of ADC channels */
adc_context_unlock_unconditionally(&data->ctx); adc_context_unlock_unconditionally(&data->ctx);
/* Configure pin-mux for ADC device */
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
LOG_ERR("ADC pinctrl setup failed (%d)", ret);
return ret;
}
return 0; return 0;
} }
BUILD_ASSERT(ARRAY_SIZE(adc_alts) == NPCX_ADC_CH_COUNT,
"The number of ADC channels and pin-mux configurations don't match!");

13
dts/arm/nuvoton/npcx7.dtsi
View file

@ -182,18 +182,9 @@
&wui_iof4 &wui_iof5 &wui_none &wui_none>; &wui_iof4 &wui_iof5 &wui_none &wui_none>;
}; };
/* Supported channels for ADC0 in npcx7 series */ /* ADC0 comparator configuration in npcx7 series */
adc0: adc@400d1000 { adc0: adc@400d1000 {
pinctrl-0 = <&alt6_adc0_sl /* ADC0 - PIN45 */ channel-count = <10>;
&alt6_adc1_sl /* ADC1 - PIN44 */
&alt6_adc2_sl /* ADC2 - PIN43 */
&alt6_adc3_sl /* ADC3 - PIN42 */
&alt6_adc4_sl /* ADC4 - PIN41 */
&altf_adc5_sl /* ADC5 - PIN37 */
&altf_adc6_sl /* ADC6 - PIN34 */
&altf_adc7_sl /* ADC7 - PINE1 */
&altf_adc8_sl /* ADC8 - PINF1 */
&altf_adc9_sl>; /* ADC9 - PINF0 */
threshold-reg-offset = <0x14>; threshold-reg-offset = <0x14>;
threshold-count = <3>; threshold-count = <3>;
}; };

15
dts/arm/nuvoton/npcx9.dtsi
View file

@ -204,20 +204,9 @@
&wui_iof4 &wui_iof5 &wui_none &wui_none>; &wui_iof4 &wui_iof5 &wui_none &wui_none>;
}; };
/* Supported channels for ADC0 in npcx9 series */ /* ADC0 comparator configuration in npcx9 series */
adc0: adc@400d1000 { adc0: adc@400d1000 {
pinctrl-0 = <&alt6_adc0_sl /* ADC0 - PIN45 */ channel-count = <12>;
&alt6_adc1_sl /* ADC1 - PIN44 */
&alt6_adc2_sl /* ADC2 - PIN43 */
&alt6_adc3_sl /* ADC3 - PIN42 */
&alt6_adc4_sl /* ADC4 - PIN41 */
&altf_adc5_sl /* ADC5 - PIN37 */
&altf_adc6_sl /* ADC6 - PIN34 */
&altf_adc7_sl /* ADC7 - PINE1 */
&altf_adc8_sl /* ADC8 - PINF1 */
&altf_adc9_sl /* ADC9 - PINF0 */
&altf_adc10_sl /* ADC10 - PINE0 */
&altf_adc11_sl>; /* ADC11 - PINC7 */
threshold-reg-offset = <0x60>; threshold-reg-offset = <0x60>;
threshold-count = <6>; threshold-count = <6>;
}; };

10
dts/bindings/iio/adc/nuvoton,npcx-adc.yaml
View file

@ -5,7 +5,7 @@ description: Nuvoton, NPCX-ADC node
compatible: "nuvoton,npcx-adc" compatible: "nuvoton,npcx-adc"
include: [adc-controller.yaml] include: [adc-controller.yaml, pinctrl-device.yaml]
properties: properties:
reg: reg:
@ -15,9 +15,13 @@ properties:
label: label:
required: true required: true
pinctrl-0: pinctrl-0:
type: phandles
required: true required: true
description: configurations of pinmux controllers pinctrl-names:
required: true
channel-count:
type: int
required: true
description: the number of ADC channels
threshold-reg-offset: threshold-reg-offset:
type: int type: int
required: true required: true