From 7ef371b2e73c5c97540850a365e0a192344be1c5 Mon Sep 17 00:00:00 2001 From: Mulin Chao Date: Mon, 21 Feb 2022 21:32:10 -0800 Subject: [PATCH] drivers: adc: add pinctrl driver support Replace soc-specific pin functions with Zephyr pinctrl api functions for pin-mux configuration in npcx adc driver. Please notice users need to configure the corresponding pinctrl nodes in 'pinctrl-0' property in the adc0 DT node. For example, if ADC0 and ADC2 channels are selected for the application, please add the follwoings in your board DT layout file. &adc0 { status = "okay"; /* Use adc0 channel 0 and 2 for 'adc_api' driver tests */ pinctrl-0 = <&adc0_chan0_gp45 &adc0_chan2_gp43>; pinctrl-names = "default"; }; Signed-off-by: Mulin Chao --- boards/arm/npcx7m6fb_evb/npcx7m6fb_evb.dts | 5 +++- boards/arm/npcx9m6f_evb/npcx9m6f_evb.dts | 5 +++- drivers/adc/adc_npcx.c | 30 +++++++++++----------- dts/arm/nuvoton/npcx7.dtsi | 13 ++-------- dts/arm/nuvoton/npcx9.dtsi | 15 ++--------- dts/bindings/iio/adc/nuvoton,npcx-adc.yaml | 10 +++++--- 6 files changed, 34 insertions(+), 44 deletions(-) diff --git a/boards/arm/npcx7m6fb_evb/npcx7m6fb_evb.dts b/boards/arm/npcx7m6fb_evb/npcx7m6fb_evb.dts index a9dc3fdec73..7be010a4eb3 100644 --- a/boards/arm/npcx7m6fb_evb/npcx7m6fb_evb.dts +++ b/boards/arm/npcx7m6fb_evb/npcx7m6fb_evb.dts @@ -82,8 +82,11 @@ }; &adc0 { - /* ADC pinmux is changed only if related channel is configured. */ status = "okay"; + /* Use adc0 channel 0 and 2 for 'adc_api' driver tests */ + pinctrl-0 = <&adc0_chan0_gp45 + &adc0_chan2_gp43>; + pinctrl-names = "default"; }; &espi0 { diff --git a/boards/arm/npcx9m6f_evb/npcx9m6f_evb.dts b/boards/arm/npcx9m6f_evb/npcx9m6f_evb.dts index 643d9411ddc..c1a07020844 100644 --- a/boards/arm/npcx9m6f_evb/npcx9m6f_evb.dts +++ b/boards/arm/npcx9m6f_evb/npcx9m6f_evb.dts @@ -95,8 +95,11 @@ }; &adc0 { - /* ADC pinmux is changed only if related channel is configured. */ status = "okay"; + /* Use adc0 channel 0 and 2 for 'adc_api' driver tests */ + pinctrl-0 = <&adc0_chan0_gp45 + &adc0_chan2_gp43>; + pinctrl-names = "default"; }; &espi0 { diff --git a/drivers/adc/adc_npcx.c b/drivers/adc/adc_npcx.c index 1feb73896ad..9b45c4cb32b 100644 --- a/drivers/adc/adc_npcx.c +++ b/drivers/adc/adc_npcx.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -26,7 +27,7 @@ LOG_MODULE_REGISTER(adc_npcx, CONFIG_ADC_LOG_LEVEL); #define ADC_REGULAR_MEAST_VAL 0x0001 /* ADC channel number */ -#define NPCX_ADC_CH_COUNT DT_INST_NUM_PINCTRLS_BY_IDX(0, 0) +#define NPCX_ADC_CH_COUNT DT_INST_PROP(0, channel_count) /* ADC targeted operating frequency (2MHz) */ #define NPCX_ADC_CLK 2000000 @@ -49,12 +50,11 @@ struct adc_npcx_config { uintptr_t base; /* clock configuration */ struct npcx_clk_cfg clk_cfg; - /* pinmux configuration */ - const struct npcx_alt *alts_list; /* amount of thresholds supported */ const uint8_t threshold_count; /* threshold control register offset */ const uint16_t threshold_reg_offset; + const struct pinctrl_dev_config *pcfg; }; struct adc_npcx_threshold_control { @@ -328,7 +328,6 @@ static void adc_context_update_buffer_pointer(struct adc_context *ctx, static int adc_npcx_channel_setup(const struct device *dev, const struct adc_channel_cfg *channel_cfg) { - const struct adc_npcx_config *const config = dev->config; uint8_t channel_id = channel_cfg->channel_id; if (channel_id >= NPCX_ADC_CH_COUNT) { @@ -356,13 +355,7 @@ static int adc_npcx_channel_setup(const struct device *dev, return -ENOTSUP; } - /* Configure pin-mux for ADC channel */ - npcx_pinctrl_mux_configure(config->alts_list + channel_cfg->channel_id, - 1, 1); - LOG_DBG("ADC channel %d, alts(%d,%d)", channel_cfg->channel_id, - config->alts_list[channel_cfg->channel_id].group, - config->alts_list[channel_cfg->channel_id].bit); - + LOG_DBG("ADC channel %d configured", channel_cfg->channel_id); return 0; } @@ -679,14 +672,16 @@ static const struct adc_driver_api adc_npcx_driver_api = { static int adc_npcx_init(const struct device *dev); -static const struct npcx_alt adc_alts[] = NPCX_DT_ALT_ITEMS_LIST(0); +PINCTRL_DT_INST_DEFINE(0); +BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, + "only one 'nuvoton_npcx_adc' compatible node may be present"); static const struct adc_npcx_config adc_npcx_cfg_0 = { .base = DT_INST_REG_ADDR(0), .clk_cfg = NPCX_DT_CLK_CFG_ITEM(0), - .alts_list = adc_alts, .threshold_count = DT_INST_PROP(0, threshold_count), .threshold_reg_offset = DT_INST_PROP(0, threshold_reg_offset), + .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0), }; static struct adc_npcx_threshold_data threshold_data_0; @@ -758,7 +753,12 @@ static int adc_npcx_init(const struct device *dev) /* Initialize mutex of ADC channels */ adc_context_unlock_unconditionally(&data->ctx); + /* Configure pin-mux for ADC device */ + ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); + if (ret < 0) { + LOG_ERR("ADC pinctrl setup failed (%d)", ret); + return ret; + } + return 0; } -BUILD_ASSERT(ARRAY_SIZE(adc_alts) == NPCX_ADC_CH_COUNT, - "The number of ADC channels and pin-mux configurations don't match!"); diff --git a/dts/arm/nuvoton/npcx7.dtsi b/dts/arm/nuvoton/npcx7.dtsi index 80c2bf3fd60..496dec1456b 100644 --- a/dts/arm/nuvoton/npcx7.dtsi +++ b/dts/arm/nuvoton/npcx7.dtsi @@ -182,18 +182,9 @@ &wui_iof4 &wui_iof5 &wui_none &wui_none>; }; - /* Supported channels for ADC0 in npcx7 series */ + /* ADC0 comparator configuration in npcx7 series */ adc0: adc@400d1000 { - pinctrl-0 = <&alt6_adc0_sl /* ADC0 - PIN45 */ - &alt6_adc1_sl /* ADC1 - PIN44 */ - &alt6_adc2_sl /* ADC2 - PIN43 */ - &alt6_adc3_sl /* ADC3 - PIN42 */ - &alt6_adc4_sl /* ADC4 - PIN41 */ - &altf_adc5_sl /* ADC5 - PIN37 */ - &altf_adc6_sl /* ADC6 - PIN34 */ - &altf_adc7_sl /* ADC7 - PINE1 */ - &altf_adc8_sl /* ADC8 - PINF1 */ - &altf_adc9_sl>; /* ADC9 - PINF0 */ + channel-count = <10>; threshold-reg-offset = <0x14>; threshold-count = <3>; }; diff --git a/dts/arm/nuvoton/npcx9.dtsi b/dts/arm/nuvoton/npcx9.dtsi index 0c3a9f6c59d..2b53e1024c7 100644 --- a/dts/arm/nuvoton/npcx9.dtsi +++ b/dts/arm/nuvoton/npcx9.dtsi @@ -204,20 +204,9 @@ &wui_iof4 &wui_iof5 &wui_none &wui_none>; }; - /* Supported channels for ADC0 in npcx9 series */ + /* ADC0 comparator configuration in npcx9 series */ adc0: adc@400d1000 { - pinctrl-0 = <&alt6_adc0_sl /* ADC0 - PIN45 */ - &alt6_adc1_sl /* ADC1 - PIN44 */ - &alt6_adc2_sl /* ADC2 - PIN43 */ - &alt6_adc3_sl /* ADC3 - PIN42 */ - &alt6_adc4_sl /* ADC4 - PIN41 */ - &altf_adc5_sl /* ADC5 - PIN37 */ - &altf_adc6_sl /* ADC6 - PIN34 */ - &altf_adc7_sl /* ADC7 - PINE1 */ - &altf_adc8_sl /* ADC8 - PINF1 */ - &altf_adc9_sl /* ADC9 - PINF0 */ - &altf_adc10_sl /* ADC10 - PINE0 */ - &altf_adc11_sl>; /* ADC11 - PINC7 */ + channel-count = <12>; threshold-reg-offset = <0x60>; threshold-count = <6>; }; diff --git a/dts/bindings/iio/adc/nuvoton,npcx-adc.yaml b/dts/bindings/iio/adc/nuvoton,npcx-adc.yaml index f7dd065649e..2228f312c07 100644 --- a/dts/bindings/iio/adc/nuvoton,npcx-adc.yaml +++ b/dts/bindings/iio/adc/nuvoton,npcx-adc.yaml @@ -5,7 +5,7 @@ description: Nuvoton, NPCX-ADC node compatible: "nuvoton,npcx-adc" -include: [adc-controller.yaml] +include: [adc-controller.yaml, pinctrl-device.yaml] properties: reg: @@ -15,9 +15,13 @@ properties: label: required: true pinctrl-0: - type: phandles required: true - description: configurations of pinmux controllers + pinctrl-names: + required: true + channel-count: + type: int + required: true + description: the number of ADC channels threshold-reg-offset: type: int required: true