From 7c8a23d6430af01835da5ed767522fffd18b997d Mon Sep 17 00:00:00 2001
From: Savinay Dharmappa <savinay.dharmappa@intel.com>
Date: Fri, 22 Sep 2017 00:15:14 +0530
Subject: [PATCH] dts: arc: Add dts support for arc

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
---
 arch/arc/Kconfig                              |  2 +
 .../soc/quark_se_c1000_ss/Kconfig.defconfig   |  4 +-
 arch/arc/soc/quark_se_c1000_ss/linker.ld      |  1 +
 dts/arc/quark_se_c1000_ss.dtsi                | 65 +++++++++++++++++++
 include/arch/arc/arch.h                       |  1 +
 5 files changed, 72 insertions(+), 1 deletion(-)
 create mode 100644 dts/arc/quark_se_c1000_ss.dtsi

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 9c424a43df8..b96e4b6e2fa 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -201,6 +201,7 @@ source "arch/arc/core/mpu/Kconfig"
 
 endmenu
 
+if !HAS_DTS
 config ICCM_SIZE
 	int "ICCM Size in kB"
 	help
@@ -256,6 +257,7 @@ config FLASH_BASE_ADDRESS
 	This option specifies the base address of the flash on the board.  It is
 	normally set by the board's defconfig file and the user should generally
 	avoid modifying it via the menu configuration.
+endif
 
 config CACHE_LINE_SIZE_DETECT
 	bool
diff --git a/arch/arc/soc/quark_se_c1000_ss/Kconfig.defconfig b/arch/arc/soc/quark_se_c1000_ss/Kconfig.defconfig
index 7d5cd395f08..6f212d22377 100644
--- a/arch/arc/soc/quark_se_c1000_ss/Kconfig.defconfig
+++ b/arch/arc/soc/quark_se_c1000_ss/Kconfig.defconfig
@@ -28,6 +28,7 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 config HARVARD
 	def_bool n
 
+if !HAS_DTS
 config FLASH_BASE_ADDRESS
 	default 0x40000000
 
@@ -53,6 +54,7 @@ config DCCM_BASE_ADDRESS
 
 config DCCM_SIZE
 	default 8
+endif
 
 config QMSI
 	def_bool y
@@ -266,7 +268,7 @@ endif # UART_QMSI_1
 
 endif # UART_QMSI
 
-if UART_CONSOLE
+if UART_CONSOLE && !HAS_DTS
 
 config UART_CONSOLE_ON_DEV_NAME
 	default "UART_1"
diff --git a/arch/arc/soc/quark_se_c1000_ss/linker.ld b/arch/arc/soc/quark_se_c1000_ss/linker.ld
index aa43c352d29..3423962d505 100644
--- a/arch/arc/soc/quark_se_c1000_ss/linker.ld
+++ b/arch/arc/soc/quark_se_c1000_ss/linker.ld
@@ -26,4 +26,5 @@
 #define DCCM_START		CONFIG_DCCM_BASE_ADDRESS
 #define DCCM_SIZE		CONFIG_DCCM_SIZE
 
+#include <generated_dts_board.h>
 #include <arch/arc/v2/linker.ld>
diff --git a/dts/arc/quark_se_c1000_ss.dtsi b/dts/arc/quark_se_c1000_ss.dtsi
new file mode 100644
index 00000000000..4eff14e8708
--- /dev/null
+++ b/dts/arc/quark_se_c1000_ss.dtsi
@@ -0,0 +1,65 @@
+#include "skeleton.dtsi"
+
+#define __SIZE_K(x) (x * 1024)
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "snps,arcem4";
+			reg = <1>;
+		};
+
+		core_intc: arcv2-intc@0 {
+			compatible = "snps,arcv2-intc";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	flash0: flash@40010000 {
+		reg = <0x40000000 DT_FLASH_SIZE>;
+	};
+
+	sram0: memory@a8000400 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0xa8000400 DT_SRAM_SIZE>;
+	};
+
+	dccm0: dccm@80000000 {
+		device_type = "memory";
+		compatible = "arc,dccm";
+		reg = <0x80000000 DT_DCCM_SIZE>;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		uart0: uart@b0002000 {
+			compatible = "intel,qmsi-uart";
+			reg = <0xb0002000 0x400>;
+			interrupts = <5 0>;
+			interrupt-parent = <&core_intc>;
+			label = "UART_0";
+
+			status = "disabled";
+		};
+
+		uart1: uart@b0002400 {
+			compatible = "intel,qmsi-uart";
+			reg = <0xb0002400 0x400>;
+			interrupts = <6 0>;
+			interrupt-parent = <&core_intc>;
+			label = "UART_1";
+
+			status = "disabled";
+		};
+	};
+};
diff --git a/include/arch/arc/arch.h b/include/arch/arc/arch.h
index ebd9c811640..9d505d88383 100644
--- a/include/arch/arc/arch.h
+++ b/include/arch/arc/arch.h
@@ -25,6 +25,7 @@ extern "C" {
 #define OCTET_TO_SIZEOFUNIT(X) (X)
 #define SIZEOFUNIT_TO_OCTET(X) (X)
 
+#include <generated_dts_board.h>
 #include <sw_isr_table.h>
 #ifdef CONFIG_CPU_ARCV2
 #include <arch/arc/v2/exc.h>