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soc: psoc6: update pinctrl for PSoC6 MCU (legacy)

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update pinctrl for PSoC6 MCU (legacy)

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
This commit is contained in:
Nazar Palamar 2024-05-14 11:37:43 +03:00 • committed by Alberto Escolar
commit 7c3b66eac8
23 changed files with 972 additions and 359 deletions
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1
soc/infineon/cat1a/CMakeLists.txt
View file

@ -21,7 +21,6 @@ endif()
if(CONFIG_SOC_FAMILY_PSOC6_LEGACY)
zephyr_include_directories(psoc6_legacy)
zephyr_sources(psoc6_legacy/soc.c)
zephyr_sources(psoc6_legacy/soc_gpio.c)
zephyr_linker_sources(NOINIT psoc6_legacy/noinit.ld)
zephyr_linker_sources(RWDATA psoc6_legacy/rwdata.ld)

126
soc/infineon/cat1a/psoc6_legacy/pinctrl_soc.h Normal file
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@ -0,0 +1,126 @@
/*
* Copyright (c) 2016-2017 Piotr Mienkowski
* Copyright (c) 2021 ATL Electronics
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
*/
/**
* @brief Infineon CAT1 SoC specific helpers for pinctrl driver.
*/
#ifndef ZEPHYR_SOC_ARM_INFINEON_CAT1_COMMON_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_INFINEON_CAT1_COMMON_PINCTRL_SOC_H_
#include <stdint.h>
#include <zephyr/devicetree.h>
#ifdef __cplusplus
extern "C" {
#endif
/** @cond INTERNAL_HIDDEN */
/**
* Bit definition in PINMUX field
*/
#define SOC_PINMUX_PORT_MASK GENMASK(7, 0)
#define SOC_PINMUX_PIN_MASK GENMASK(15, 8)
#define SOC_PINMUX_HSIOM_MASK GENMASK(23, 16)
#define SOC_PINMUX_SIGNAL_MASK GENMASK(31, 24)
/*
* Pin flags/attributes
*/
#define SOC_GPIO_DEFAULT (0)
#define SOC_GPIO_FLAGS_POS (0)
#define SOC_GPIO_FLAGS_MASK GENMASK(6, 0)
#define SOC_GPIO_PULLUP_POS (0)
#define SOC_GPIO_PULLUP BIT(SOC_GPIO_PULLUP_POS)
#define SOC_GPIO_PULLDOWN_POS (1)
#define SOC_GPIO_PULLDOWN BIT(SOC_GPIO_PULLDOWN_POS)
#define SOC_GPIO_OPENDRAIN_POS (2)
#define SOC_GPIO_OPENDRAIN BIT(SOC_GPIO_OPENDRAIN_POS)
#define SOC_GPIO_OPENSOURCE_POS (3)
#define SOC_GPIO_OPENSOURCE BIT(SOC_GPIO_OPENSOURCE_POS)
/* Push-Pull means Strong, see dts/pinctrl/pincfg-node.yaml */
#define SOC_GPIO_PUSHPULL_POS (4)
#define SOC_GPIO_PUSHPULL BIT(SOC_GPIO_PUSHPULL_POS)
/* Input-Enable means Input-Buffer, see dts/pinctrl/pincfg-node.yaml */
#define SOC_GPIO_INPUTENABLE_POS (5)
#define SOC_GPIO_INPUTENABLE BIT(SOC_GPIO_INPUTENABLE_POS)
#define SOC_GPIO_HIGHZ_POS (6)
#define SOC_GPIO_HIGHZ BIT(SOC_GPIO_HIGHZ_POS)
/** Type for CAT1 Soc pin. */
typedef struct {
/**
* Pinmux settings (port, pin and function).
* [0..7] - Port nunder
* [8..15] - Pin number
* [16..23]- HSIOM function
*/
uint32_t pinmux;
/** Pin configuration (bias, drive and slew rate). */
uint32_t pincfg;
} pinctrl_soc_pin_t;
#define CAT1_PINMUX_GET_PORT_NUM(pinmux) FIELD_GET(SOC_PINMUX_PORT_MASK, pinmux)
#define CAT1_PINMUX_GET_PIN_NUM(pinmux) FIELD_GET(SOC_PINMUX_PIN_MASK, pinmux)
#define CAT1_PINMUX_GET_HSIOM_FUNC(pinmux) FIELD_GET(SOC_PINMUX_HSIOM_MASK, pinmux)
/**
* @brief Utility macro to initialize pinmux field in #pinctrl_pin_t.
* @param node_id Node identifier.
*/
#define Z_PINCTRL_CAT1_PINMUX_INIT(node_id) DT_PROP(node_id, pinmux)
/**
* @brief Utility macro to initialize pincfg field in #pinctrl_pin_t.
* @param node_id Node identifier.
*/
#define Z_PINCTRL_CAT1_PINCFG_INIT(node_id) ( \
(DT_PROP(node_id, bias_pull_up) << SOC_GPIO_PULLUP_POS) | \
(DT_PROP(node_id, bias_pull_down) << SOC_GPIO_PULLDOWN_POS) | \
(DT_PROP(node_id, drive_open_drain) << SOC_GPIO_OPENDRAIN_POS) | \
(DT_PROP(node_id, drive_open_source) << SOC_GPIO_OPENSOURCE_POS) | \
(DT_PROP(node_id, drive_push_pull) << SOC_GPIO_PUSHPULL_POS) | \
(DT_PROP(node_id, input_enable) << SOC_GPIO_INPUTENABLE_POS) | \
(DT_PROP(node_id, bias_high_impedance) << SOC_GPIO_HIGHZ_POS))
/**
* @brief Utility macro to initialize each pin.
*
* @param node_id Node identifier.
* @param state_prop State property name.
* @param idx State property entry index.
*/
#define Z_PINCTRL_STATE_PIN_INIT(node_id, state_prop, idx) \
{ .pinmux = Z_PINCTRL_CAT1_PINMUX_INIT( \
DT_PROP_BY_IDX(node_id, state_prop, idx)), \
.pincfg = Z_PINCTRL_CAT1_PINCFG_INIT( \
DT_PROP_BY_IDX(node_id, state_prop, idx)) },
/**
* @brief Utility macro to initialize state pins contained in a given property.
*
* @param node_id Node identifier.
* @param prop Property name describing state pins.
*/
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
{ DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT) }
/** @endcond */
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_SOC_ARM_INFINEON_CAT1_COMMON_PINCTRL_SOC_H_ */

1
soc/infineon/cat1a/psoc6_legacy/soc.h
View file

@ -20,7 +20,6 @@
#ifndef _ASMLANGUAGE
#include <cy_device_headers.h>
#include "soc_gpio.h"
#include "cypress_psoc6_dt.h"
#endif /* !_ASMLANGUAGE */

59
soc/infineon/cat1a/psoc6_legacy/soc_gpio.c
View file

@ -1,59 +0,0 @@
/*
* Copyright (c) 2016 Piotr Mienkowski
* Copyright (c) 2021 ATL Electronics
* SPDX-License-Identifier: Apache-2.0
*/
/** @file
* @brief Cypress PSoC-6 MCU family General Purpose Input Output (GPIO)
* module HAL driver.
*/
#include "soc_gpio.h"
#include "cy_gpio.h"
static uint32_t soc_gpio_get_drv_mode(uint32_t flags)
{
uint32_t drv_mode = CY_GPIO_DM_ANALOG;
flags = ((flags & SOC_GPIO_FLAGS_MASK) >> SOC_GPIO_FLAGS_POS);
if (flags & SOC_GPIO_OPENDRAIN) {
drv_mode = CY_GPIO_DM_OD_DRIVESLOW_IN_OFF;
} else if (flags & SOC_GPIO_OPENSOURCE) {
drv_mode = CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF;
} else if (flags & SOC_GPIO_PUSHPULL) {
drv_mode = CY_GPIO_DM_STRONG_IN_OFF;
} else if ((flags & SOC_GPIO_PULLUP) && (flags & SOC_GPIO_PULLDOWN)) {
drv_mode = CY_GPIO_DM_PULLUP_DOWN_IN_OFF;
} else if (flags & SOC_GPIO_PULLUP) {
drv_mode = CY_GPIO_DM_PULLUP_IN_OFF;
} else if (flags & SOC_GPIO_PULLDOWN) {
drv_mode = CY_GPIO_DM_PULLDOWN_IN_OFF;
} else {
;
}
if (flags & SOC_GPIO_INPUTENABLE) {
drv_mode |= CY_GPIO_DM_HIGHZ;
}
return drv_mode;
}
void soc_gpio_configure(const struct soc_gpio_pin *pin)
{
uint32_t drv_mode = soc_gpio_get_drv_mode(pin->flags);
uint32_t function = ((pin->flags & SOC_GPIO_FUNC_MASK) >>
SOC_GPIO_FUNC_POS);
Cy_GPIO_SetHSIOM(pin->regs, pin->pinum, function);
Cy_GPIO_SetDrivemode(pin->regs, pin->pinum, drv_mode);
}
void soc_gpio_list_configure(const struct soc_gpio_pin pins[], size_t size)
{
for (size_t i = 0; i < size; i++) {
soc_gpio_configure(&pins[i]);
}
}

99
soc/infineon/cat1a/psoc6_legacy/soc_gpio.h
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@ -1,99 +0,0 @@
/*
* Copyright (c) 2016-2017 Piotr Mienkowski
* Copyright (c) 2021 ATL Electronics
* SPDX-License-Identifier: Apache-2.0
*/
/** @file
* @brief Cypress PSoC-6 MCU family General Purpose Input Output (GPIO)
* module HAL driver.
*/
#ifndef _CYPRESS_PSOC6_SOC_GPIO_H_
#define _CYPRESS_PSOC6_SOC_GPIO_H_
#include <zephyr/types.h>
#include <soc.h>
/*
* Pin flags/attributes
*/
#define SOC_GPIO_DEFAULT (0)
#define SOC_GPIO_FLAGS_POS (0)
#define SOC_GPIO_FLAGS_MASK (0x3F << SOC_GPIO_FLAGS_POS)
#define SOC_GPIO_PULLUP_POS (0)
#define SOC_GPIO_PULLUP (1 << SOC_GPIO_PULLUP_POS)
#define SOC_GPIO_PULLDOWN_POS (1)
#define SOC_GPIO_PULLDOWN (1 << SOC_GPIO_PULLDOWN_POS)
#define SOC_GPIO_OPENDRAIN_POS (2)
#define SOC_GPIO_OPENDRAIN (1 << SOC_GPIO_OPENDRAIN_POS)
#define SOC_GPIO_OPENSOURCE_POS (3)
#define SOC_GPIO_OPENSOURCE (1 << SOC_GPIO_OPENSOURCE_POS)
/* Push-Pull means Strong, see dts/pinctrl/pincfg-node.yaml */
#define SOC_GPIO_PUSHPULL_POS (4)
#define SOC_GPIO_PUSHPULL (1 << SOC_GPIO_PUSHPULL_POS)
/* Input-Enable means Input-Buffer, see dts/pinctrl/pincfg-node.yaml */
#define SOC_GPIO_INPUTENABLE_POS (5)
#define SOC_GPIO_INPUTENABLE (1 << SOC_GPIO_INPUTENABLE_POS)
/* Bit field: SOC_GPIO_IN_FILTER */
#define SOC_GPIO_IN_FILTER_POS (6)
#define SOC_GPIO_IN_FILTER_MASK (3 << SOC_GPIO_IN_FILTER_POS)
#define SOC_GPIO_IN_FILTER_NONE (0 << SOC_GPIO_IN_FILTER_POS)
#define SOC_GPIO_IN_FILTER_DEBOUNCE (1 << SOC_GPIO_IN_FILTER_POS)
#define SOC_GPIO_IN_FILTER_DEGLITCH (2 << SOC_GPIO_IN_FILTER_POS)
#define SOC_GPIO_INT_ENABLE (1 << 8)
/* Bit field: SOC_GPIO_INT_TRIG */
#define SOC_GPIO_INT_TRIG_POS (9)
#define SOC_GPIO_INT_TRIG_MASK (3 << SOC_GPIO_INT_TRIG_POS)
/** Interrupt is triggered by a level detection event. */
#define SOC_GPIO_INT_TRIG_LEVEL (0 << SOC_GPIO_INT_TRIG_POS)
/** Interrupt is triggered by an edge detection event. */
#define SOC_GPIO_INT_TRIG_EDGE (1 << SOC_GPIO_INT_TRIG_POS)
/** Interrupt is triggered by any edge detection event. */
#define SOC_GPIO_INT_TRIG_DOUBLE_EDGE (2 << SOC_GPIO_INT_TRIG_POS)
/** Interrupt is triggered by a high level / rising edge detection event */
#define SOC_GPIO_INT_ACTIVE_HIGH (1 << 11)
/* Bit field: SOC_GPIO_FUNC */
#define SOC_GPIO_FUNC_POS (16)
#define SOC_GPIO_FUNC_MASK (0x1F << SOC_GPIO_FUNC_POS)
struct soc_gpio_pin {
GPIO_PRT_Type *regs; /** pointer to registers of the GPIO controller */
uint32_t pinum; /** pin number */
uint32_t flags; /** pin flags/attributes */
};
/**
* @brief Configure GPIO pin(s).
*
* Configure one or several pins belonging to the same GPIO port.
* Example scenarios:
* - configure pin(s) as input with debounce filter enabled.
* - connect pin(s) to a HSIOM function and enable pull-up.
* - configure pin(s) as open drain output.
* All pins are configured in the same way.
*
* @param pin pin's configuration data such as pin mask, pin attributes, etc.
*/
void soc_gpio_configure(const struct soc_gpio_pin *pin);
/**
* @brief Configure a list of GPIO pin(s).
*
* Configure an arbitrary amount of pins in an arbitrary way. Each
* configuration entry is a single item in an array passed as an
* argument to the function.
*
* @param pins an array where each item contains pin's configuration data.
* @param size size of the pin list.
*/
void soc_gpio_list_configure(const struct soc_gpio_pin pins[], size_t size);
#endif /* _CYPRESS_PSOC6_SOC_GPIO_H_ */