From 7c3b66eac85cdade79d090fc4d9360d07ce04d2b Mon Sep 17 00:00:00 2001 From: Nazar Palamar Date: Tue, 14 May 2024 11:37:43 +0300 Subject: [PATCH] soc: psoc6: update pinctrl for PSoC6 MCU (legacy) update pinctrl for PSoC6 MCU (legacy) Signed-off-by: Nazar Palamar --- .../cy8ckit_062_ble_common.dtsi | 5 +- .../cy8ckit_062_ble_cy8c6347-pinctrl.dtsi | 45 + .../cy8ckit_062_ble_cy8c6347_m0_0_0_0.overlay | 4 +- .../cy8ckit_062_ble_cy8c6347_m0_1_0_0.overlay | 10 +- .../cy8ckit_062_ble_cy8c6347_m4_0_0_0.overlay | 5 +- .../cy8ckit_062_wifi_bt_cy8c6247-pinctrl.dtsi | 45 + .../cy8ckit_062_wifi_bt_cy8c6247_m0.dts | 4 +- .../cy8ckit_062_wifi_bt_cy8c6247_m4.dts | 4 +- drivers/pinctrl/pinctrl_ifx_cat1.c | 1 - drivers/serial/Kconfig.psoc6 | 1 + drivers/serial/uart_psoc6.c | 23 +- drivers/spi/Kconfig.psoc6 | 1 + drivers/spi/spi_psoc6.c | 14 +- .../infineon/cat1a/legacy/psoc6-pinctrl.dtsi | 838 +++++++++++++++--- dts/arm/infineon/cat1a/legacy/psoc6.dtsi | 2 +- .../pinctrl/cypress,psoc6-pinctrl.yaml | 39 - dts/bindings/serial/cypress,psoc6-uart.yaml | 2 +- dts/bindings/spi/cypress,psoc6-spi.yaml | 2 +- soc/infineon/cat1a/CMakeLists.txt | 1 - soc/infineon/cat1a/psoc6_legacy/pinctrl_soc.h | 126 +++ soc/infineon/cat1a/psoc6_legacy/soc.h | 1 - soc/infineon/cat1a/psoc6_legacy/soc_gpio.c | 59 -- soc/infineon/cat1a/psoc6_legacy/soc_gpio.h | 99 --- 23 files changed, 972 insertions(+), 359 deletions(-) create mode 100644 boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347-pinctrl.dtsi create mode 100644 boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247-pinctrl.dtsi delete mode 100644 dts/bindings/pinctrl/cypress,psoc6-pinctrl.yaml create mode 100644 soc/infineon/cat1a/psoc6_legacy/pinctrl_soc.h delete mode 100644 soc/infineon/cat1a/psoc6_legacy/soc_gpio.c delete mode 100644 soc/infineon/cat1a/psoc6_legacy/soc_gpio.h diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_common.dtsi b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_common.dtsi index 437ea9ad225..764348106c9 100644 --- a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_common.dtsi +++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_common.dtsi @@ -86,7 +86,8 @@ &spi6 { cs-gpios = <&gpio_prt12 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>, - <&gpio_prt13 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + <&gpio_prt13 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - pinctrl-0 = <&p12_0_spi6_mosi &p12_1_spi6_miso &p12_2_spi6_clk>; + pinctrl-0 = <&p12_0_scb6_spi_m_mosi &p12_1_scb6_spi_m_miso &p12_2_scb6_spi_m_clk>; + pinctrl-names = "default"; }; diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347-pinctrl.dtsi b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347-pinctrl.dtsi new file mode 100644 index 00000000000..1e42a6e4646 --- /dev/null +++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347-pinctrl.dtsi @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/* Configure pin control bias mode for uart5 pins */ +&p5_1_scb5_uart_tx { + drive-push-pull; +}; + +&p5_0_scb5_uart_rx { + input-enable; +}; + +&p9_1_scb2_uart_tx { + drive-push-pull; +}; + +&p9_0_scb2_uart_rx { + input-enable; +}; + +&p13_1_scb6_uart_tx { + drive-push-pull; +}; + +&p13_0_scb6_uart_rx { + input-enable; +}; + +/* Configure pin control bias mode for SPI pins */ +&p12_0_scb6_spi_m_mosi { + drive-push-pull; +}; + +&p12_1_scb6_spi_m_miso { + input-enable; +}; + +&p12_2_scb6_spi_m_clk { + drive-push-pull; +}; diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.overlay b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.overlay index eab076f247c..9ef0f747cd0 100644 --- a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.overlay +++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.overlay @@ -3,6 +3,7 @@ * * SPDX-License-Identifier: Apache-2.0 */ +#include "cy8ckit_062_ble_cy8c6347-pinctrl.dtsi" / { aliases { @@ -21,7 +22,8 @@ interrupt-parent = <&intmux_ch21>; - pinctrl-0 = <&p5_0_uart5_rx &p5_1_uart5_tx>; + pinctrl-0 = <&p5_0_scb5_uart_rx &p5_1_scb5_uart_tx>; + pinctrl-names = "default"; }; arduino_serial: &uart5 {}; diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.overlay b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.overlay index 49944a6dea4..ea63d017a65 100644 --- a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.overlay +++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.overlay @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include "cy8ckit_062_ble_cy8c6347-pinctrl.dtsi" + / { aliases { uart-2 = &uart2; @@ -21,7 +23,9 @@ interrupt-parent = <&intmux_ch21>; - pinctrl-0 = <&p9_0_uart2_rx &p9_1_uart2_tx>; + pinctrl-0 = <&p9_0_scb2_uart_rx &p9_1_scb2_uart_tx>; + pinctrl-names = "default"; + }; &uart5 { @@ -30,7 +34,9 @@ interrupt-parent = <&intmux_ch22>; - pinctrl-0 = <&p5_0_uart5_rx &p5_1_uart5_tx>; + pinctrl-0 = <&p5_0_scb5_uart_rx &p5_1_scb5_uart_tx>; + pinctrl-names = "default"; + }; arduino_serial: &uart5 {}; diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.overlay b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.overlay index 9284d41cea7..26f422a9b4d 100644 --- a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.overlay +++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.overlay @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include "cy8ckit_062_ble_cy8c6347-pinctrl.dtsi" + / { aliases { uart-6 = &uart6; @@ -19,5 +21,6 @@ status = "okay"; current-speed = <115200>; - pinctrl-0 = <&p13_0_uart6_rx &p13_1_uart6_tx>; + pinctrl-0 = <&p13_0_scb6_uart_rx &p13_1_scb6_uart_tx>; + pinctrl-names = "default"; }; diff --git a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247-pinctrl.dtsi b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247-pinctrl.dtsi new file mode 100644 index 00000000000..1e42a6e4646 --- /dev/null +++ b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247-pinctrl.dtsi @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/* Configure pin control bias mode for uart5 pins */ +&p5_1_scb5_uart_tx { + drive-push-pull; +}; + +&p5_0_scb5_uart_rx { + input-enable; +}; + +&p9_1_scb2_uart_tx { + drive-push-pull; +}; + +&p9_0_scb2_uart_rx { + input-enable; +}; + +&p13_1_scb6_uart_tx { + drive-push-pull; +}; + +&p13_0_scb6_uart_rx { + input-enable; +}; + +/* Configure pin control bias mode for SPI pins */ +&p12_0_scb6_spi_m_mosi { + drive-push-pull; +}; + +&p12_1_scb6_spi_m_miso { + input-enable; +}; + +&p12_2_scb6_spi_m_clk { + drive-push-pull; +}; diff --git a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.dts b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.dts index 18fe196201b..73766b76c10 100644 --- a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.dts +++ b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.dts @@ -9,6 +9,7 @@ #include #include +#include "cy8ckit_062_wifi_bt_cy8c6247-pinctrl.dtsi" / { model = "cy8ckit_062_wifi_bt_m0 with a Cypress PSoC6 SoC"; @@ -61,5 +62,6 @@ interrupt-parent = <&intmux_ch21>; - pinctrl-0 = <&p13_0_uart6_rx &p13_1_uart6_tx>; + pinctrl-0 = <&p13_0_scb6_uart_rx &p13_1_scb6_uart_tx>; + pinctrl-names = "default"; }; diff --git a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.dts b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.dts index 7cd87ba8634..29ea4b85134 100644 --- a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.dts +++ b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.dts @@ -7,6 +7,7 @@ /dts-v1/; #include +#include "cy8ckit_062_wifi_bt_cy8c6247-pinctrl.dtsi" / { model = "cy8ckit_062_wifi_bt_m4 with a Cypress PSoC6 SoC"; @@ -28,5 +29,6 @@ status = "okay"; current-speed = <115200>; - pinctrl-0 = <&p5_0_uart5_rx &p5_1_uart5_tx>; + pinctrl-0 = <&p5_0_scb5_uart_rx &p5_1_scb5_uart_tx>; + pinctrl-names = "default"; }; diff --git a/drivers/pinctrl/pinctrl_ifx_cat1.c b/drivers/pinctrl/pinctrl_ifx_cat1.c index dbeaab855f3..d1806346a8f 100644 --- a/drivers/pinctrl/pinctrl_ifx_cat1.c +++ b/drivers/pinctrl/pinctrl_ifx_cat1.c @@ -10,7 +10,6 @@ */ #include -#include #include #define GPIO_PORT_OR_NULL(node_id) \ diff --git a/drivers/serial/Kconfig.psoc6 b/drivers/serial/Kconfig.psoc6 index 66981e3766c..4f0bb2c8fca 100644 --- a/drivers/serial/Kconfig.psoc6 +++ b/drivers/serial/Kconfig.psoc6 @@ -11,5 +11,6 @@ config UART_PSOC6 select SERIAL_HAS_DRIVER select SERIAL_SUPPORT_INTERRUPT select USE_INFINEON_UART + select PINCTRL help This option enables the SCB[UART] driver for PSoC-6 SoC family. diff --git a/drivers/serial/uart_psoc6.c b/drivers/serial/uart_psoc6.c index 6bf09b22b71..fa46d8a8224 100644 --- a/drivers/serial/uart_psoc6.c +++ b/drivers/serial/uart_psoc6.c @@ -12,12 +12,8 @@ * - Error handling is not implemented. * - The driver works only in polling mode, interrupt mode is not implemented. */ -#include -#include -#include -#include -#include #include +#include #include "cy_syslib.h" #include "cy_sysclk.h" @@ -50,8 +46,7 @@ struct cypress_psoc6_config { #ifdef CONFIG_UART_INTERRUPT_DRIVEN uart_irq_config_func_t irq_config_func; #endif - uint32_t num_pins; - struct soc_gpio_pin pins[]; + const struct pinctrl_dev_config *pcfg; }; #ifdef CONFIG_UART_INTERRUPT_DRIVEN @@ -104,9 +99,14 @@ static const cy_stc_scb_uart_config_t uartConfig = { */ static int uart_psoc6_init(const struct device *dev) { + int ret; const struct cypress_psoc6_config *config = dev->config; - soc_gpio_list_configure(config->pins, config->num_pins); + /* Configure dt provided device signals when available */ + ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); + if (ret < 0) { + return ret; + } /* Connect assigned divider to be a clock source for UART */ Cy_SysClk_PeriphAssignDivider(config->periph_id, @@ -344,14 +344,11 @@ static const struct uart_driver_api uart_psoc6_driver_api = { #endif #define CY_PSOC6_UART_INIT(n) \ - CY_PSOC6_UART_DECL_DATA(n) \ - CY_PSOC6_UART_IRQ_FUNC(n) \ + PINCTRL_DT_INST_DEFINE(n); \ static const struct cypress_psoc6_config cy_psoc6_uart##n##_config = { \ .base = (CySCB_Type *)DT_INST_REG_ADDR(n), \ .periph_id = DT_INST_PROP(n, peripheral_id), \ - \ - .num_pins = CY_PSOC6_DT_INST_NUM_PINS(n), \ - .pins = CY_PSOC6_DT_INST_PINS(n), \ + .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ \ CY_PSOC6_UART_IRQ_SET_FUNC(n) \ }; \ diff --git a/drivers/spi/Kconfig.psoc6 b/drivers/spi/Kconfig.psoc6 index 21b4bfe596b..5b7fe353d81 100644 --- a/drivers/spi/Kconfig.psoc6 +++ b/drivers/spi/Kconfig.psoc6 @@ -8,5 +8,6 @@ config SPI_PSOC6 default y depends on DT_HAS_CYPRESS_PSOC6_SPI_ENABLED select USE_INFINEON_SPI + select PINCTRL help This option enables the SCB[SPI] driver for PSoC-6 SoC family. diff --git a/drivers/spi/spi_psoc6.c b/drivers/spi/spi_psoc6.c index 7b6a30d3a65..817c94899b2 100644 --- a/drivers/spi/spi_psoc6.c +++ b/drivers/spi/spi_psoc6.c @@ -31,8 +31,7 @@ struct spi_psoc6_config { CySCB_Type *base; uint32_t periph_id; void (*irq_config_func)(const struct device *dev); - uint32_t num_pins; - struct soc_gpio_pin pins[]; + const struct pinctrl_dev_config *pcfg; }; struct spi_psoc6_transfer { @@ -377,7 +376,12 @@ static int spi_psoc6_init(const struct device *dev) const struct spi_psoc6_config *config = dev->config; struct spi_psoc6_data *data = dev->data; - soc_gpio_list_configure(config->pins, config->num_pins); + + /* Configure dt provided device signals when available */ + err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); + if (ret < 0) { + return ret; + } Cy_SysClk_PeriphAssignDivider(config->periph_id, CY_SYSCLK_DIV_8_BIT, @@ -408,12 +412,12 @@ static const struct spi_driver_api spi_psoc6_driver_api = { }; #define SPI_PSOC6_DEVICE_INIT(n) \ + PINCTRL_DT_INST_DEFINE(n); \ static void spi_psoc6_spi##n##_irq_cfg(const struct device *port); \ static const struct spi_psoc6_config spi_psoc6_config_##n = { \ .base = (CySCB_Type *)DT_INST_REG_ADDR(n), \ .periph_id = DT_INST_PROP(n, peripheral_id), \ - .num_pins = CY_PSOC6_DT_INST_NUM_PINS(n), \ - .pins = CY_PSOC6_DT_INST_PINS(n), \ + .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ .irq_config_func = spi_psoc6_spi##n##_irq_cfg, \ }; \ static struct spi_psoc6_data spi_psoc6_dev_data_##n = { \ diff --git a/dts/arm/infineon/cat1a/legacy/psoc6-pinctrl.dtsi b/dts/arm/infineon/cat1a/legacy/psoc6-pinctrl.dtsi index 526f74eea03..2f06ed2269f 100644 --- a/dts/arm/infineon/cat1a/legacy/psoc6-pinctrl.dtsi +++ b/dts/arm/infineon/cat1a/legacy/psoc6-pinctrl.dtsi @@ -4,140 +4,718 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "pinctrl_cypress_psoc6.h" +#include +#include / { soc { - pinctrl@40310000 { - /* instance, signal, port, pin, hsiom [, flag1, ... ] */ - DT_CYPRESS_HSIOM(spi0, mosi, 0, 2, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi0, miso, 0, 3, act_8, input-enable); - DT_CYPRESS_HSIOM(spi0, clk, 0, 4, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi0, sel0, 0, 5, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi0, sel1, 0, 0, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi0, sel2, 0, 1, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi1, mosi, 10, 0, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi1, miso, 10, 1, act_8, input-enable); - DT_CYPRESS_HSIOM(spi1, clk, 10, 2, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi1, sel0, 10, 3, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi1, sel1, 10, 4, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi1, sel2, 10, 5, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi1, sel3, 10, 6, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi2, mosi, 9, 0, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi2, miso, 9, 1, act_8, input-enable); - DT_CYPRESS_HSIOM(spi2, clk, 9, 2, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi2, sel0, 9, 3, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi2, sel1, 9, 4, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi2, sel2, 9, 5, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi2, sel3, 9, 6, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi3, mosi, 6, 0, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi3, miso, 6, 1, act_8, input-enable); - DT_CYPRESS_HSIOM(spi3, clk, 6, 2, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi3, sel0, 6, 3, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi3, sel1, 7, 7, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi3, sel2, 8, 7, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi3, sel3, 5, 7, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi4, mosi, 7, 0, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi4, miso, 7, 1, act_8, input-enable); - DT_CYPRESS_HSIOM(spi4, clk, 7, 2, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi4, sel0, 7, 3, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi4, sel1, 7, 4, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi4, sel2, 7, 5, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi4, sel3, 7, 6, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi4, mosi, 8, 0, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi4, miso, 8, 1, act_8, input-enable); - DT_CYPRESS_HSIOM(spi4, clk, 8, 2, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi4, sel0, 8, 3, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi4, sel1, 8, 4, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi4, sel2, 8, 5, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi4, sel3, 8, 6, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi5, mosi, 5, 0, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi5, miso, 5, 1, act_8, input-enable); - DT_CYPRESS_HSIOM(spi5, clk, 5, 2, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi5, sel0, 5, 3, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi5, sel1, 5, 4, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi5, sel2, 5, 5, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi5, sel3, 5, 6, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi5, mosi, 11, 0, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi5, miso, 11, 1, act_8, input-enable); - DT_CYPRESS_HSIOM(spi5, clk, 11, 2, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi5, sel0, 11, 3, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi5, sel1, 11, 4, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi5, sel2, 11, 5, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi5, sel3, 11, 6, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi6, mosi, 6, 4, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi6, miso, 6, 5, act_8, input-enable); - DT_CYPRESS_HSIOM(spi6, clk, 6, 6, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi6, sel0, 6, 7, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi6, mosi, 12, 0, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi6, miso, 12, 1, act_8, input-enable); - DT_CYPRESS_HSIOM(spi6, clk, 12, 2, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi6, sel0, 12, 3, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi6, sel1, 12, 4, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi6, sel2, 12, 5, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi6, sel3, 12, 6, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi6, mosi, 13, 0, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi6, miso, 13, 1, act_8, input-enable); - DT_CYPRESS_HSIOM(spi6, clk, 13, 2, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi6, sel0, 13, 3, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi6, sel1, 13, 4, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi6, sel2, 13, 5, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi6, sel3, 13, 6, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi7, mosi, 1, 0, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi7, miso, 1, 1, act_8, input-enable); - DT_CYPRESS_HSIOM(spi7, clk, 1, 2, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi7, sel0, 1, 3, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi7, sel1, 1, 4, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(spi7, sel2, 1, 5, act_8, drive-push-pull); - DT_CYPRESS_HSIOM(uart0, rx, 0, 2, act_6, input-enable); - DT_CYPRESS_HSIOM(uart0, tx, 0, 3, act_6, drive-push-pull); - DT_CYPRESS_HSIOM(uart0, rts, 0, 4, act_6, drive-push-pull); - DT_CYPRESS_HSIOM(uart0, cts, 0, 5, act_6, input-enable); - DT_CYPRESS_HSIOM(uart1, rx, 10, 0, act_6, input-enable); - DT_CYPRESS_HSIOM(uart1, tx, 10, 1, act_6, drive-push-pull); - DT_CYPRESS_HSIOM(uart1, rts, 10, 2, act_6, drive-push-pull); - DT_CYPRESS_HSIOM(uart1, cts, 10, 3, act_6, input-enable); - DT_CYPRESS_HSIOM(uart2, rx, 9, 0, act_6, input-enable); - DT_CYPRESS_HSIOM(uart2, tx, 9, 1, act_6, drive-push-pull); - DT_CYPRESS_HSIOM(uart2, rts, 9, 2, act_6, drive-push-pull); - DT_CYPRESS_HSIOM(uart2, cts, 9, 3, act_6, input-enable); - DT_CYPRESS_HSIOM(uart3, rx, 6, 0, act_6, input-enable); - DT_CYPRESS_HSIOM(uart3, tx, 6, 1, act_6, drive-push-pull); - DT_CYPRESS_HSIOM(uart3, rts, 6, 2, act_6, drive-push-pull); - DT_CYPRESS_HSIOM(uart3, cts, 6, 3, act_6, input-enable); - DT_CYPRESS_HSIOM(uart4, rx, 7, 0, act_6, input-enable); - DT_CYPRESS_HSIOM(uart4, tx, 7, 1, act_6, drive-push-pull); - DT_CYPRESS_HSIOM(uart4, rts, 7, 2, act_6, drive-push-pull); - DT_CYPRESS_HSIOM(uart4, cts, 7, 3, act_6, input-enable); - DT_CYPRESS_HSIOM(uart4, rx, 8, 0, act_6, input-enable); - DT_CYPRESS_HSIOM(uart4, tx, 8, 1, act_6, drive-push-pull); - DT_CYPRESS_HSIOM(uart4, rts, 8, 2, act_6, drive-push-pull); - DT_CYPRESS_HSIOM(uart4, cts, 8, 3, act_6, input-enable); - DT_CYPRESS_HSIOM(uart5, rx, 5, 0, act_6, input-enable); - DT_CYPRESS_HSIOM(uart5, tx, 5, 1, act_6, drive-push-pull); - DT_CYPRESS_HSIOM(uart5, rts, 5, 2, act_6, drive-push-pull); - DT_CYPRESS_HSIOM(uart5, cts, 5, 3, act_6, input-enable); - DT_CYPRESS_HSIOM(uart5, rx, 11, 0, act_6, input-enable); - DT_CYPRESS_HSIOM(uart5, tx, 11, 1, act_6, drive-push-pull); - DT_CYPRESS_HSIOM(uart5, rts, 11, 2, act_6, drive-push-pull); - DT_CYPRESS_HSIOM(uart5, cts, 11, 3, act_6, input-enable); - DT_CYPRESS_HSIOM(uart6, rx, 6, 4, act_6, input-enable); - DT_CYPRESS_HSIOM(uart6, tx, 6, 5, act_6, drive-push-pull); - DT_CYPRESS_HSIOM(uart6, rts, 6, 6, act_6, drive-push-pull); - DT_CYPRESS_HSIOM(uart6, cts, 6, 7, act_6, input-enable); - DT_CYPRESS_HSIOM(uart6, rx, 12, 0, act_6, input-enable); - DT_CYPRESS_HSIOM(uart6, tx, 12, 1, act_6, drive-push-pull); - DT_CYPRESS_HSIOM(uart6, rts, 12, 2, act_6, drive-push-pull); - DT_CYPRESS_HSIOM(uart6, cts, 12, 3, act_6, input-enable); - DT_CYPRESS_HSIOM(uart6, rx, 13, 0, act_6, input-enable); - DT_CYPRESS_HSIOM(uart6, tx, 13, 1, act_6, drive-push-pull); - DT_CYPRESS_HSIOM(uart6, rts, 13, 2, act_6, drive-push-pull); - DT_CYPRESS_HSIOM(uart6, cts, 13, 3, act_6, input-enable); - DT_CYPRESS_HSIOM(uart7, rx, 1, 0, act_6, input-enable); - DT_CYPRESS_HSIOM(uart7, tx, 1, 1, act_6, drive-push-pull); - DT_CYPRESS_HSIOM(uart7, rts, 1, 2, act_6, drive-push-pull); - DT_CYPRESS_HSIOM(uart7, cts, 1, 3, act_6, input-enable); + pinctrl: pinctrl@40310000 { + /* scb_i2c_scl */ + /omit-if-no-ref/ p0_2_scb0_i2c_scl: p0_2_scb0_i2c_scl { + pinmux = ; + }; + /omit-if-no-ref/ p1_0_scb7_i2c_scl: p1_0_scb7_i2c_scl { + pinmux = ; + }; + /omit-if-no-ref/ p5_0_scb5_i2c_scl: p5_0_scb5_i2c_scl { + pinmux = ; + }; + /omit-if-no-ref/ p6_0_scb3_i2c_scl: p6_0_scb3_i2c_scl { + pinmux = ; + }; + /omit-if-no-ref/ p6_0_scb8_i2c_scl: p6_0_scb8_i2c_scl { + pinmux = ; + }; + /omit-if-no-ref/ p6_4_scb6_i2c_scl: p6_4_scb6_i2c_scl { + pinmux = ; + }; + /omit-if-no-ref/ p6_4_scb8_i2c_scl: p6_4_scb8_i2c_scl { + pinmux = ; + }; + /omit-if-no-ref/ p7_0_scb4_i2c_scl: p7_0_scb4_i2c_scl { + pinmux = ; + }; + /omit-if-no-ref/ p8_0_scb4_i2c_scl: p8_0_scb4_i2c_scl { + pinmux = ; + }; + /omit-if-no-ref/ p9_0_scb2_i2c_scl: p9_0_scb2_i2c_scl { + pinmux = ; + }; + /omit-if-no-ref/ p10_0_scb1_i2c_scl: p10_0_scb1_i2c_scl { + pinmux = ; + }; + /omit-if-no-ref/ p11_0_scb5_i2c_scl: p11_0_scb5_i2c_scl { + pinmux = ; + }; + /omit-if-no-ref/ p12_0_scb6_i2c_scl: p12_0_scb6_i2c_scl { + pinmux = ; + }; + /omit-if-no-ref/ p13_0_scb6_i2c_scl: p13_0_scb6_i2c_scl { + pinmux = ; + }; + + /* scb_i2c_sda */ + /omit-if-no-ref/ p0_3_scb0_i2c_sda: p0_3_scb0_i2c_sda { + pinmux = ; + }; + /omit-if-no-ref/ p1_1_scb7_i2c_sda: p1_1_scb7_i2c_sda { + pinmux = ; + }; + /omit-if-no-ref/ p5_1_scb5_i2c_sda: p5_1_scb5_i2c_sda { + pinmux = ; + }; + /omit-if-no-ref/ p6_1_scb3_i2c_sda: p6_1_scb3_i2c_sda { + pinmux = ; + }; + /omit-if-no-ref/ p6_1_scb8_i2c_sda: p6_1_scb8_i2c_sda { + pinmux = ; + }; + /omit-if-no-ref/ p6_5_scb6_i2c_sda: p6_5_scb6_i2c_sda { + pinmux = ; + }; + /omit-if-no-ref/ p6_5_scb8_i2c_sda: p6_5_scb8_i2c_sda { + pinmux = ; + }; + /omit-if-no-ref/ p7_1_scb4_i2c_sda: p7_1_scb4_i2c_sda { + pinmux = ; + }; + /omit-if-no-ref/ p8_1_scb4_i2c_sda: p8_1_scb4_i2c_sda { + pinmux = ; + }; + /omit-if-no-ref/ p9_1_scb2_i2c_sda: p9_1_scb2_i2c_sda { + pinmux = ; + }; + /omit-if-no-ref/ p10_1_scb1_i2c_sda: p10_1_scb1_i2c_sda { + pinmux = ; + }; + /omit-if-no-ref/ p11_1_scb5_i2c_sda: p11_1_scb5_i2c_sda { + pinmux = ; + }; + /omit-if-no-ref/ p12_1_scb6_i2c_sda: p12_1_scb6_i2c_sda { + pinmux = ; + }; + /omit-if-no-ref/ p13_1_scb6_i2c_sda: p13_1_scb6_i2c_sda { + pinmux = ; + }; + + /* scb_spi_m_clk */ + /omit-if-no-ref/ p0_4_scb0_spi_m_clk: p0_4_scb0_spi_m_clk { + pinmux = ; + }; + /omit-if-no-ref/ p5_2_scb5_spi_m_clk: p5_2_scb5_spi_m_clk { + pinmux = ; + }; + /omit-if-no-ref/ p6_2_scb3_spi_m_clk: p6_2_scb3_spi_m_clk { + pinmux = ; + }; + /omit-if-no-ref/ p6_2_scb8_spi_m_clk: p6_2_scb8_spi_m_clk { + pinmux = ; + }; + /omit-if-no-ref/ p6_6_scb6_spi_m_clk: p6_6_scb6_spi_m_clk { + pinmux = ; + }; + /omit-if-no-ref/ p6_6_scb8_spi_m_clk: p6_6_scb8_spi_m_clk { + pinmux = ; + }; + /omit-if-no-ref/ p7_2_scb4_spi_m_clk: p7_2_scb4_spi_m_clk { + pinmux = ; + }; + /omit-if-no-ref/ p8_2_scb4_spi_m_clk: p8_2_scb4_spi_m_clk { + pinmux = ; + }; + /omit-if-no-ref/ p9_2_scb2_spi_m_clk: p9_2_scb2_spi_m_clk { + pinmux = ; + }; + /omit-if-no-ref/ p10_2_scb1_spi_m_clk: p10_2_scb1_spi_m_clk { + pinmux = ; + }; + /omit-if-no-ref/ p11_2_scb5_spi_m_clk: p11_2_scb5_spi_m_clk { + pinmux = ; + }; + /omit-if-no-ref/ p12_2_scb6_spi_m_clk: p12_2_scb6_spi_m_clk { + pinmux = ; + }; + + /* scb_spi_m_miso */ + /omit-if-no-ref/ p0_3_scb0_spi_m_miso: p0_3_scb0_spi_m_miso { + pinmux = ; + }; + /omit-if-no-ref/ p1_1_scb7_spi_m_miso: p1_1_scb7_spi_m_miso { + pinmux = ; + }; + /omit-if-no-ref/ p5_1_scb5_spi_m_miso: p5_1_scb5_spi_m_miso { + pinmux = ; + }; + /omit-if-no-ref/ p6_1_scb3_spi_m_miso: p6_1_scb3_spi_m_miso { + pinmux = ; + }; + /omit-if-no-ref/ p6_1_scb8_spi_m_miso: p6_1_scb8_spi_m_miso { + pinmux = ; + }; + /omit-if-no-ref/ p6_5_scb6_spi_m_miso: p6_5_scb6_spi_m_miso { + pinmux = ; + }; + /omit-if-no-ref/ p6_5_scb8_spi_m_miso: p6_5_scb8_spi_m_miso { + pinmux = ; + }; + /omit-if-no-ref/ p7_1_scb4_spi_m_miso: p7_1_scb4_spi_m_miso { + pinmux = ; + }; + /omit-if-no-ref/ p8_1_scb4_spi_m_miso: p8_1_scb4_spi_m_miso { + pinmux = ; + }; + /omit-if-no-ref/ p9_1_scb2_spi_m_miso: p9_1_scb2_spi_m_miso { + pinmux = ; + }; + /omit-if-no-ref/ p10_1_scb1_spi_m_miso: p10_1_scb1_spi_m_miso { + pinmux = ; + }; + /omit-if-no-ref/ p11_1_scb5_spi_m_miso: p11_1_scb5_spi_m_miso { + pinmux = ; + }; + /omit-if-no-ref/ p12_1_scb6_spi_m_miso: p12_1_scb6_spi_m_miso { + pinmux = ; + }; + /omit-if-no-ref/ p13_1_scb6_spi_m_miso: p13_1_scb6_spi_m_miso { + pinmux = ; + }; + + /* scb_spi_m_mosi */ + /omit-if-no-ref/ p0_2_scb0_spi_m_mosi: p0_2_scb0_spi_m_mosi { + pinmux = ; + }; + /omit-if-no-ref/ p1_0_scb7_spi_m_mosi: p1_0_scb7_spi_m_mosi { + pinmux = ; + }; + /omit-if-no-ref/ p5_0_scb5_spi_m_mosi: p5_0_scb5_spi_m_mosi { + pinmux = ; + }; + /omit-if-no-ref/ p6_0_scb3_spi_m_mosi: p6_0_scb3_spi_m_mosi { + pinmux = ; + }; + /omit-if-no-ref/ p6_0_scb8_spi_m_mosi: p6_0_scb8_spi_m_mosi { + pinmux = ; + }; + /omit-if-no-ref/ p6_4_scb6_spi_m_mosi: p6_4_scb6_spi_m_mosi { + pinmux = ; + }; + /omit-if-no-ref/ p6_4_scb8_spi_m_mosi: p6_4_scb8_spi_m_mosi { + pinmux = ; + }; + /omit-if-no-ref/ p7_0_scb4_spi_m_mosi: p7_0_scb4_spi_m_mosi { + pinmux = ; + }; + /omit-if-no-ref/ p8_0_scb4_spi_m_mosi: p8_0_scb4_spi_m_mosi { + pinmux = ; + }; + /omit-if-no-ref/ p9_0_scb2_spi_m_mosi: p9_0_scb2_spi_m_mosi { + pinmux = ; + }; + /omit-if-no-ref/ p10_0_scb1_spi_m_mosi: p10_0_scb1_spi_m_mosi { + pinmux = ; + }; + /omit-if-no-ref/ p11_0_scb5_spi_m_mosi: p11_0_scb5_spi_m_mosi { + pinmux = ; + }; + /omit-if-no-ref/ p12_0_scb6_spi_m_mosi: p12_0_scb6_spi_m_mosi { + pinmux = ; + }; + /omit-if-no-ref/ p13_0_scb6_spi_m_mosi: p13_0_scb6_spi_m_mosi { + pinmux = ; + }; + + /* scb_spi_m_select0 */ + /omit-if-no-ref/ p0_5_scb0_spi_m_select0: p0_5_scb0_spi_m_select0 { + pinmux = ; + }; + /omit-if-no-ref/ p5_3_scb5_spi_m_select0: p5_3_scb5_spi_m_select0 { + pinmux = ; + }; + /omit-if-no-ref/ p6_3_scb3_spi_m_select0: p6_3_scb3_spi_m_select0 { + pinmux = ; + }; + /omit-if-no-ref/ p6_3_scb8_spi_m_select0: p6_3_scb8_spi_m_select0 { + pinmux = ; + }; + /omit-if-no-ref/ p6_7_scb6_spi_m_select0: p6_7_scb6_spi_m_select0 { + pinmux = ; + }; + /omit-if-no-ref/ p6_7_scb8_spi_m_select0: p6_7_scb8_spi_m_select0 { + pinmux = ; + }; + /omit-if-no-ref/ p7_3_scb4_spi_m_select0: p7_3_scb4_spi_m_select0 { + pinmux = ; + }; + /omit-if-no-ref/ p8_3_scb4_spi_m_select0: p8_3_scb4_spi_m_select0 { + pinmux = ; + }; + /omit-if-no-ref/ p9_3_scb2_spi_m_select0: p9_3_scb2_spi_m_select0 { + pinmux = ; + }; + /omit-if-no-ref/ p10_3_scb1_spi_m_select0: p10_3_scb1_spi_m_select0 { + pinmux = ; + }; + /omit-if-no-ref/ p11_3_scb5_spi_m_select0: p11_3_scb5_spi_m_select0 { + pinmux = ; + }; + /omit-if-no-ref/ p12_3_scb6_spi_m_select0: p12_3_scb6_spi_m_select0 { + pinmux = ; + }; + + /* scb_spi_m_select1 */ + /omit-if-no-ref/ p0_0_scb0_spi_m_select1: p0_0_scb0_spi_m_select1 { + pinmux = ; + }; + /omit-if-no-ref/ p1_4_scb7_spi_m_select1: p1_4_scb7_spi_m_select1 { + pinmux = ; + }; + /omit-if-no-ref/ p5_4_scb5_spi_m_select1: p5_4_scb5_spi_m_select1 { + pinmux = ; + }; + /omit-if-no-ref/ p7_4_scb4_spi_m_select1: p7_4_scb4_spi_m_select1 { + pinmux = ; + }; + /omit-if-no-ref/ p7_7_scb3_spi_m_select1: p7_7_scb3_spi_m_select1 { + pinmux = ; + }; + /omit-if-no-ref/ p8_4_scb4_spi_m_select1: p8_4_scb4_spi_m_select1 { + pinmux = ; + }; + /omit-if-no-ref/ p10_4_scb1_spi_m_select1: p10_4_scb1_spi_m_select1 { + pinmux = ; + }; + /omit-if-no-ref/ p11_4_scb5_spi_m_select1: p11_4_scb5_spi_m_select1 { + pinmux = ; + }; + /omit-if-no-ref/ p12_4_scb6_spi_m_select1: p12_4_scb6_spi_m_select1 { + pinmux = ; + }; + + /* scb_spi_m_select2 */ + /omit-if-no-ref/ p0_1_scb0_spi_m_select2: p0_1_scb0_spi_m_select2 { + pinmux = ; + }; + /omit-if-no-ref/ p1_5_scb7_spi_m_select2: p1_5_scb7_spi_m_select2 { + pinmux = ; + }; + /omit-if-no-ref/ p5_5_scb5_spi_m_select2: p5_5_scb5_spi_m_select2 { + pinmux = ; + }; + /omit-if-no-ref/ p7_5_scb4_spi_m_select2: p7_5_scb4_spi_m_select2 { + pinmux = ; + }; + /omit-if-no-ref/ p8_5_scb4_spi_m_select2: p8_5_scb4_spi_m_select2 { + pinmux = ; + }; + /omit-if-no-ref/ p8_7_scb3_spi_m_select2: p8_7_scb3_spi_m_select2 { + pinmux = ; + }; + /omit-if-no-ref/ p10_5_scb1_spi_m_select2: p10_5_scb1_spi_m_select2 { + pinmux = ; + }; + /omit-if-no-ref/ p11_5_scb5_spi_m_select2: p11_5_scb5_spi_m_select2 { + pinmux = ; + }; + + /* scb_spi_m_select3 */ + /omit-if-no-ref/ p5_6_scb5_spi_m_select3: p5_6_scb5_spi_m_select3 { + pinmux = ; + }; + /omit-if-no-ref/ p5_7_scb3_spi_m_select3: p5_7_scb3_spi_m_select3 { + pinmux = ; + }; + /omit-if-no-ref/ p7_6_scb4_spi_m_select3: p7_6_scb4_spi_m_select3 { + pinmux = ; + }; + /omit-if-no-ref/ p8_6_scb4_spi_m_select3: p8_6_scb4_spi_m_select3 { + pinmux = ; + }; + /omit-if-no-ref/ p10_6_scb1_spi_m_select3: p10_6_scb1_spi_m_select3 { + pinmux = ; + }; + /omit-if-no-ref/ p11_6_scb5_spi_m_select3: p11_6_scb5_spi_m_select3 { + pinmux = ; + }; + + /* scb_spi_s_clk */ + /omit-if-no-ref/ p0_4_scb0_spi_s_clk: p0_4_scb0_spi_s_clk { + pinmux = ; + }; + /omit-if-no-ref/ p5_2_scb5_spi_s_clk: p5_2_scb5_spi_s_clk { + pinmux = ; + }; + /omit-if-no-ref/ p6_2_scb3_spi_s_clk: p6_2_scb3_spi_s_clk { + pinmux = ; + }; + /omit-if-no-ref/ p6_2_scb8_spi_s_clk: p6_2_scb8_spi_s_clk { + pinmux = ; + }; + /omit-if-no-ref/ p6_6_scb6_spi_s_clk: p6_6_scb6_spi_s_clk { + pinmux = ; + }; + /omit-if-no-ref/ p6_6_scb8_spi_s_clk: p6_6_scb8_spi_s_clk { + pinmux = ; + }; + /omit-if-no-ref/ p7_2_scb4_spi_s_clk: p7_2_scb4_spi_s_clk { + pinmux = ; + }; + /omit-if-no-ref/ p8_2_scb4_spi_s_clk: p8_2_scb4_spi_s_clk { + pinmux = ; + }; + /omit-if-no-ref/ p9_2_scb2_spi_s_clk: p9_2_scb2_spi_s_clk { + pinmux = ; + }; + /omit-if-no-ref/ p10_2_scb1_spi_s_clk: p10_2_scb1_spi_s_clk { + pinmux = ; + }; + /omit-if-no-ref/ p11_2_scb5_spi_s_clk: p11_2_scb5_spi_s_clk { + pinmux = ; + }; + /omit-if-no-ref/ p12_2_scb6_spi_s_clk: p12_2_scb6_spi_s_clk { + pinmux = ; + }; + + /* scb_spi_s_miso */ + /omit-if-no-ref/ p0_3_scb0_spi_s_miso: p0_3_scb0_spi_s_miso { + pinmux = ; + }; + /omit-if-no-ref/ p1_1_scb7_spi_s_miso: p1_1_scb7_spi_s_miso { + pinmux = ; + }; + /omit-if-no-ref/ p5_1_scb5_spi_s_miso: p5_1_scb5_spi_s_miso { + pinmux = ; + }; + /omit-if-no-ref/ p6_1_scb3_spi_s_miso: p6_1_scb3_spi_s_miso { + pinmux = ; + }; + /omit-if-no-ref/ p6_1_scb8_spi_s_miso: p6_1_scb8_spi_s_miso { + pinmux = ; + }; + /omit-if-no-ref/ p6_5_scb6_spi_s_miso: p6_5_scb6_spi_s_miso { + pinmux = ; + }; + /omit-if-no-ref/ p6_5_scb8_spi_s_miso: p6_5_scb8_spi_s_miso { + pinmux = ; + }; + /omit-if-no-ref/ p7_1_scb4_spi_s_miso: p7_1_scb4_spi_s_miso { + pinmux = ; + }; + /omit-if-no-ref/ p8_1_scb4_spi_s_miso: p8_1_scb4_spi_s_miso { + pinmux = ; + }; + /omit-if-no-ref/ p9_1_scb2_spi_s_miso: p9_1_scb2_spi_s_miso { + pinmux = ; + }; + /omit-if-no-ref/ p10_1_scb1_spi_s_miso: p10_1_scb1_spi_s_miso { + pinmux = ; + }; + /omit-if-no-ref/ p11_1_scb5_spi_s_miso: p11_1_scb5_spi_s_miso { + pinmux = ; + }; + /omit-if-no-ref/ p12_1_scb6_spi_s_miso: p12_1_scb6_spi_s_miso { + pinmux = ; + }; + /omit-if-no-ref/ p13_1_scb6_spi_s_miso: p13_1_scb6_spi_s_miso { + pinmux = ; + }; + + /* scb_spi_s_mosi */ + /omit-if-no-ref/ p0_2_scb0_spi_s_mosi: p0_2_scb0_spi_s_mosi { + pinmux = ; + }; + /omit-if-no-ref/ p1_0_scb7_spi_s_mosi: p1_0_scb7_spi_s_mosi { + pinmux = ; + }; + /omit-if-no-ref/ p5_0_scb5_spi_s_mosi: p5_0_scb5_spi_s_mosi { + pinmux = ; + }; + /omit-if-no-ref/ p6_0_scb3_spi_s_mosi: p6_0_scb3_spi_s_mosi { + pinmux = ; + }; + /omit-if-no-ref/ p6_0_scb8_spi_s_mosi: p6_0_scb8_spi_s_mosi { + pinmux = ; + }; + /omit-if-no-ref/ p6_4_scb6_spi_s_mosi: p6_4_scb6_spi_s_mosi { + pinmux = ; + }; + /omit-if-no-ref/ p6_4_scb8_spi_s_mosi: p6_4_scb8_spi_s_mosi { + pinmux = ; + }; + /omit-if-no-ref/ p7_0_scb4_spi_s_mosi: p7_0_scb4_spi_s_mosi { + pinmux = ; + }; + /omit-if-no-ref/ p8_0_scb4_spi_s_mosi: p8_0_scb4_spi_s_mosi { + pinmux = ; + }; + /omit-if-no-ref/ p9_0_scb2_spi_s_mosi: p9_0_scb2_spi_s_mosi { + pinmux = ; + }; + /omit-if-no-ref/ p10_0_scb1_spi_s_mosi: p10_0_scb1_spi_s_mosi { + pinmux = ; + }; + /omit-if-no-ref/ p11_0_scb5_spi_s_mosi: p11_0_scb5_spi_s_mosi { + pinmux = ; + }; + /omit-if-no-ref/ p12_0_scb6_spi_s_mosi: p12_0_scb6_spi_s_mosi { + pinmux = ; + }; + /omit-if-no-ref/ p13_0_scb6_spi_s_mosi: p13_0_scb6_spi_s_mosi { + pinmux = ; + }; + + /* scb_spi_s_select0 */ + /omit-if-no-ref/ p0_5_scb0_spi_s_select0: p0_5_scb0_spi_s_select0 { + pinmux = ; + }; + /omit-if-no-ref/ p5_3_scb5_spi_s_select0: p5_3_scb5_spi_s_select0 { + pinmux = ; + }; + /omit-if-no-ref/ p6_3_scb3_spi_s_select0: p6_3_scb3_spi_s_select0 { + pinmux = ; + }; + /omit-if-no-ref/ p6_3_scb8_spi_s_select0: p6_3_scb8_spi_s_select0 { + pinmux = ; + }; + /omit-if-no-ref/ p6_7_scb6_spi_s_select0: p6_7_scb6_spi_s_select0 { + pinmux = ; + }; + /omit-if-no-ref/ p6_7_scb8_spi_s_select0: p6_7_scb8_spi_s_select0 { + pinmux = ; + }; + /omit-if-no-ref/ p7_3_scb4_spi_s_select0: p7_3_scb4_spi_s_select0 { + pinmux = ; + }; + /omit-if-no-ref/ p8_3_scb4_spi_s_select0: p8_3_scb4_spi_s_select0 { + pinmux = ; + }; + /omit-if-no-ref/ p9_3_scb2_spi_s_select0: p9_3_scb2_spi_s_select0 { + pinmux = ; + }; + /omit-if-no-ref/ p10_3_scb1_spi_s_select0: p10_3_scb1_spi_s_select0 { + pinmux = ; + }; + /omit-if-no-ref/ p11_3_scb5_spi_s_select0: p11_3_scb5_spi_s_select0 { + pinmux = ; + }; + /omit-if-no-ref/ p12_3_scb6_spi_s_select0: p12_3_scb6_spi_s_select0 { + pinmux = ; + }; + + /* scb_spi_s_select1 */ + /omit-if-no-ref/ p0_0_scb0_spi_s_select1: p0_0_scb0_spi_s_select1 { + pinmux = ; + }; + /omit-if-no-ref/ p1_4_scb7_spi_s_select1: p1_4_scb7_spi_s_select1 { + pinmux = ; + }; + /omit-if-no-ref/ p5_4_scb5_spi_s_select1: p5_4_scb5_spi_s_select1 { + pinmux = ; + }; + /omit-if-no-ref/ p7_4_scb4_spi_s_select1: p7_4_scb4_spi_s_select1 { + pinmux = ; + }; + /omit-if-no-ref/ p7_7_scb3_spi_s_select1: p7_7_scb3_spi_s_select1 { + pinmux = ; + }; + /omit-if-no-ref/ p8_4_scb4_spi_s_select1: p8_4_scb4_spi_s_select1 { + pinmux = ; + }; + /omit-if-no-ref/ p10_4_scb1_spi_s_select1: p10_4_scb1_spi_s_select1 { + pinmux = ; + }; + /omit-if-no-ref/ p11_4_scb5_spi_s_select1: p11_4_scb5_spi_s_select1 { + pinmux = ; + }; + /omit-if-no-ref/ p12_4_scb6_spi_s_select1: p12_4_scb6_spi_s_select1 { + pinmux = ; + }; + + /* scb_spi_s_select2 */ + /omit-if-no-ref/ p0_1_scb0_spi_s_select2: p0_1_scb0_spi_s_select2 { + pinmux = ; + }; + /omit-if-no-ref/ p1_5_scb7_spi_s_select2: p1_5_scb7_spi_s_select2 { + pinmux = ; + }; + /omit-if-no-ref/ p5_5_scb5_spi_s_select2: p5_5_scb5_spi_s_select2 { + pinmux = ; + }; + /omit-if-no-ref/ p7_5_scb4_spi_s_select2: p7_5_scb4_spi_s_select2 { + pinmux = ; + }; + /omit-if-no-ref/ p8_5_scb4_spi_s_select2: p8_5_scb4_spi_s_select2 { + pinmux = ; + }; + /omit-if-no-ref/ p8_7_scb3_spi_s_select2: p8_7_scb3_spi_s_select2 { + pinmux = ; + }; + /omit-if-no-ref/ p10_5_scb1_spi_s_select2: p10_5_scb1_spi_s_select2 { + pinmux = ; + }; + /omit-if-no-ref/ p11_5_scb5_spi_s_select2: p11_5_scb5_spi_s_select2 { + pinmux = ; + }; + + /* scb_spi_s_select3 */ + /omit-if-no-ref/ p5_6_scb5_spi_s_select3: p5_6_scb5_spi_s_select3 { + pinmux = ; + }; + /omit-if-no-ref/ p5_7_scb3_spi_s_select3: p5_7_scb3_spi_s_select3 { + pinmux = ; + }; + /omit-if-no-ref/ p7_6_scb4_spi_s_select3: p7_6_scb4_spi_s_select3 { + pinmux = ; + }; + /omit-if-no-ref/ p8_6_scb4_spi_s_select3: p8_6_scb4_spi_s_select3 { + pinmux = ; + }; + /omit-if-no-ref/ p10_6_scb1_spi_s_select3: p10_6_scb1_spi_s_select3 { + pinmux = ; + }; + /omit-if-no-ref/ p11_6_scb5_spi_s_select3: p11_6_scb5_spi_s_select3 { + pinmux = ; + }; + + /* scb_uart_cts */ + /omit-if-no-ref/ p0_5_scb0_uart_cts: p0_5_scb0_uart_cts { + pinmux = ; + }; + /omit-if-no-ref/ p5_3_scb5_uart_cts: p5_3_scb5_uart_cts { + pinmux = ; + }; + /omit-if-no-ref/ p6_3_scb3_uart_cts: p6_3_scb3_uart_cts { + pinmux = ; + }; + /omit-if-no-ref/ p6_7_scb6_uart_cts: p6_7_scb6_uart_cts { + pinmux = ; + }; + /omit-if-no-ref/ p7_3_scb4_uart_cts: p7_3_scb4_uart_cts { + pinmux = ; + }; + /omit-if-no-ref/ p8_3_scb4_uart_cts: p8_3_scb4_uart_cts { + pinmux = ; + }; + /omit-if-no-ref/ p9_3_scb2_uart_cts: p9_3_scb2_uart_cts { + pinmux = ; + }; + /omit-if-no-ref/ p10_3_scb1_uart_cts: p10_3_scb1_uart_cts { + pinmux = ; + }; + /omit-if-no-ref/ p11_3_scb5_uart_cts: p11_3_scb5_uart_cts { + pinmux = ; + }; + /omit-if-no-ref/ p12_3_scb6_uart_cts: p12_3_scb6_uart_cts { + pinmux = ; + }; + + /* scb_uart_rts */ + /omit-if-no-ref/ p0_4_scb0_uart_rts: p0_4_scb0_uart_rts { + pinmux = ; + }; + /omit-if-no-ref/ p5_2_scb5_uart_rts: p5_2_scb5_uart_rts { + pinmux = ; + }; + /omit-if-no-ref/ p6_2_scb3_uart_rts: p6_2_scb3_uart_rts { + pinmux = ; + }; + /omit-if-no-ref/ p6_6_scb6_uart_rts: p6_6_scb6_uart_rts { + pinmux = ; + }; + /omit-if-no-ref/ p7_2_scb4_uart_rts: p7_2_scb4_uart_rts { + pinmux = ; + }; + /omit-if-no-ref/ p8_2_scb4_uart_rts: p8_2_scb4_uart_rts { + pinmux = ; + }; + /omit-if-no-ref/ p9_2_scb2_uart_rts: p9_2_scb2_uart_rts { + pinmux = ; + }; + /omit-if-no-ref/ p10_2_scb1_uart_rts: p10_2_scb1_uart_rts { + pinmux = ; + }; + /omit-if-no-ref/ p11_2_scb5_uart_rts: p11_2_scb5_uart_rts { + pinmux = ; + }; + /omit-if-no-ref/ p12_2_scb6_uart_rts: p12_2_scb6_uart_rts { + pinmux = ; + }; + + /* scb_uart_rx */ + /omit-if-no-ref/ p0_2_scb0_uart_rx: p0_2_scb0_uart_rx { + pinmux = ; + }; + /omit-if-no-ref/ p1_0_scb7_uart_rx: p1_0_scb7_uart_rx { + pinmux = ; + }; + /omit-if-no-ref/ p5_0_scb5_uart_rx: p5_0_scb5_uart_rx { + pinmux = ; + }; + /omit-if-no-ref/ p6_0_scb3_uart_rx: p6_0_scb3_uart_rx { + pinmux = ; + }; + /omit-if-no-ref/ p6_4_scb6_uart_rx: p6_4_scb6_uart_rx { + pinmux = ; + }; + /omit-if-no-ref/ p7_0_scb4_uart_rx: p7_0_scb4_uart_rx { + pinmux = ; + }; + /omit-if-no-ref/ p8_0_scb4_uart_rx: p8_0_scb4_uart_rx { + pinmux = ; + }; + /omit-if-no-ref/ p9_0_scb2_uart_rx: p9_0_scb2_uart_rx { + pinmux = ; + }; + /omit-if-no-ref/ p10_0_scb1_uart_rx: p10_0_scb1_uart_rx { + pinmux = ; + }; + /omit-if-no-ref/ p11_0_scb5_uart_rx: p11_0_scb5_uart_rx { + pinmux = ; + }; + /omit-if-no-ref/ p12_0_scb6_uart_rx: p12_0_scb6_uart_rx { + pinmux = ; + }; + /omit-if-no-ref/ p13_0_scb6_uart_rx: p13_0_scb6_uart_rx { + pinmux = ; + }; + + /* scb_uart_tx */ + /omit-if-no-ref/ p0_3_scb0_uart_tx: p0_3_scb0_uart_tx { + pinmux = ; + }; + /omit-if-no-ref/ p1_1_scb7_uart_tx: p1_1_scb7_uart_tx { + pinmux = ; + }; + /omit-if-no-ref/ p5_1_scb5_uart_tx: p5_1_scb5_uart_tx { + pinmux = ; + }; + /omit-if-no-ref/ p6_1_scb3_uart_tx: p6_1_scb3_uart_tx { + pinmux = ; + }; + /omit-if-no-ref/ p6_5_scb6_uart_tx: p6_5_scb6_uart_tx { + pinmux = ; + }; + /omit-if-no-ref/ p7_1_scb4_uart_tx: p7_1_scb4_uart_tx { + pinmux = ; + }; + /omit-if-no-ref/ p8_1_scb4_uart_tx: p8_1_scb4_uart_tx { + pinmux = ; + }; + /omit-if-no-ref/ p9_1_scb2_uart_tx: p9_1_scb2_uart_tx { + pinmux = ; + }; + /omit-if-no-ref/ p10_1_scb1_uart_tx: p10_1_scb1_uart_tx { + pinmux = ; + }; + /omit-if-no-ref/ p11_1_scb5_uart_tx: p11_1_scb5_uart_tx { + pinmux = ; + }; + /omit-if-no-ref/ p12_1_scb6_uart_tx: p12_1_scb6_uart_tx { + pinmux = ; + }; + /omit-if-no-ref/ p13_1_scb6_uart_tx: p13_1_scb6_uart_tx { + pinmux = ; + }; }; }; }; diff --git a/dts/arm/infineon/cat1a/legacy/psoc6.dtsi b/dts/arm/infineon/cat1a/legacy/psoc6.dtsi index a6ab61e9949..ad9fef2e0fd 100644 --- a/dts/arm/infineon/cat1a/legacy/psoc6.dtsi +++ b/dts/arm/infineon/cat1a/legacy/psoc6.dtsi @@ -67,7 +67,7 @@ soc { pinctrl@40310000 { - compatible = "cypress,psoc6-pinctrl"; + compatible = "infineon,cat1-pinctrl"; #address-cells = <1>; #size-cells = <1>; ranges = <0x40310000 0x40310000 0x2024>; diff --git a/dts/bindings/pinctrl/cypress,psoc6-pinctrl.yaml b/dts/bindings/pinctrl/cypress,psoc6-pinctrl.yaml deleted file mode 100644 index 8914f873f81..00000000000 --- a/dts/bindings/pinctrl/cypress,psoc6-pinctrl.yaml +++ /dev/null @@ -1,39 +0,0 @@ -# Copyright (c) 2020, Linaro Limited -# Copyright (c) 2021, ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -description: | - Cypress PSoC-6 Pinctrl container node - - The Cypress PSoC-6 pins implements following pin configuration option: - - * bias-pull-up - * bias-pull-down - * drive-open-drain - * drive-open-source - * drive-push-pull (strong) - * input-enable (input-buffer) - - These options define devicetree flags that are converted to SoC flags at - CY_PSOC6_PIN_FLAGS(). - -compatible: "cypress,psoc6-pinctrl" - -include: base.yaml - -properties: - "#address-cells": - required: true - const: 1 - "#size-cells": - required: true - const: 1 - -child-binding: - description: cypress pins - - include: pincfg-node.yaml - - properties: - "cypress,pins": - type: phandle-array diff --git a/dts/bindings/serial/cypress,psoc6-uart.yaml b/dts/bindings/serial/cypress,psoc6-uart.yaml index 543975ab7c8..6cf83bce617 100644 --- a/dts/bindings/serial/cypress,psoc6-uart.yaml +++ b/dts/bindings/serial/cypress,psoc6-uart.yaml @@ -6,7 +6,7 @@ description: Cypress SCB[UART] compatible: "cypress,psoc6-uart" -include: uart-controller.yaml +include: [uart-controller.yaml, pinctrl-device.yaml] properties: reg: diff --git a/dts/bindings/spi/cypress,psoc6-spi.yaml b/dts/bindings/spi/cypress,psoc6-spi.yaml index 81a12f44ec5..bebdc53d314 100644 --- a/dts/bindings/spi/cypress,psoc6-spi.yaml +++ b/dts/bindings/spi/cypress,psoc6-spi.yaml @@ -5,7 +5,7 @@ description: Cypress SBC[SPI] compatible: "cypress,psoc6-spi" -include: spi-controller.yaml +include: [spi-controller.yaml, pinctrl-device.yaml] properties: reg: diff --git a/soc/infineon/cat1a/CMakeLists.txt b/soc/infineon/cat1a/CMakeLists.txt index c08c13ac0cc..fa77e29d0ce 100644 --- a/soc/infineon/cat1a/CMakeLists.txt +++ b/soc/infineon/cat1a/CMakeLists.txt @@ -21,7 +21,6 @@ endif() if(CONFIG_SOC_FAMILY_PSOC6_LEGACY) zephyr_include_directories(psoc6_legacy) zephyr_sources(psoc6_legacy/soc.c) - zephyr_sources(psoc6_legacy/soc_gpio.c) zephyr_linker_sources(NOINIT psoc6_legacy/noinit.ld) zephyr_linker_sources(RWDATA psoc6_legacy/rwdata.ld) diff --git a/soc/infineon/cat1a/psoc6_legacy/pinctrl_soc.h b/soc/infineon/cat1a/psoc6_legacy/pinctrl_soc.h new file mode 100644 index 00000000000..30316fe87e8 --- /dev/null +++ b/soc/infineon/cat1a/psoc6_legacy/pinctrl_soc.h @@ -0,0 +1,126 @@ +/* + * Copyright (c) 2016-2017 Piotr Mienkowski + * Copyright (c) 2021 ATL Electronics + * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +/** + * @brief Infineon CAT1 SoC specific helpers for pinctrl driver. + */ + +#ifndef ZEPHYR_SOC_ARM_INFINEON_CAT1_COMMON_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_ARM_INFINEON_CAT1_COMMON_PINCTRL_SOC_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** @cond INTERNAL_HIDDEN */ + +/** + * Bit definition in PINMUX field + */ +#define SOC_PINMUX_PORT_MASK GENMASK(7, 0) +#define SOC_PINMUX_PIN_MASK GENMASK(15, 8) +#define SOC_PINMUX_HSIOM_MASK GENMASK(23, 16) +#define SOC_PINMUX_SIGNAL_MASK GENMASK(31, 24) + +/* + * Pin flags/attributes + */ +#define SOC_GPIO_DEFAULT (0) +#define SOC_GPIO_FLAGS_POS (0) +#define SOC_GPIO_FLAGS_MASK GENMASK(6, 0) +#define SOC_GPIO_PULLUP_POS (0) +#define SOC_GPIO_PULLUP BIT(SOC_GPIO_PULLUP_POS) +#define SOC_GPIO_PULLDOWN_POS (1) +#define SOC_GPIO_PULLDOWN BIT(SOC_GPIO_PULLDOWN_POS) +#define SOC_GPIO_OPENDRAIN_POS (2) +#define SOC_GPIO_OPENDRAIN BIT(SOC_GPIO_OPENDRAIN_POS) +#define SOC_GPIO_OPENSOURCE_POS (3) +#define SOC_GPIO_OPENSOURCE BIT(SOC_GPIO_OPENSOURCE_POS) + +/* Push-Pull means Strong, see dts/pinctrl/pincfg-node.yaml */ +#define SOC_GPIO_PUSHPULL_POS (4) +#define SOC_GPIO_PUSHPULL BIT(SOC_GPIO_PUSHPULL_POS) + +/* Input-Enable means Input-Buffer, see dts/pinctrl/pincfg-node.yaml */ +#define SOC_GPIO_INPUTENABLE_POS (5) +#define SOC_GPIO_INPUTENABLE BIT(SOC_GPIO_INPUTENABLE_POS) + +#define SOC_GPIO_HIGHZ_POS (6) +#define SOC_GPIO_HIGHZ BIT(SOC_GPIO_HIGHZ_POS) + +/** Type for CAT1 Soc pin. */ +typedef struct { + /** + * Pinmux settings (port, pin and function). + * [0..7] - Port nunder + * [8..15] - Pin number + * [16..23]- HSIOM function + */ + uint32_t pinmux; + + /** Pin configuration (bias, drive and slew rate). */ + uint32_t pincfg; +} pinctrl_soc_pin_t; + +#define CAT1_PINMUX_GET_PORT_NUM(pinmux) FIELD_GET(SOC_PINMUX_PORT_MASK, pinmux) +#define CAT1_PINMUX_GET_PIN_NUM(pinmux) FIELD_GET(SOC_PINMUX_PIN_MASK, pinmux) +#define CAT1_PINMUX_GET_HSIOM_FUNC(pinmux) FIELD_GET(SOC_PINMUX_HSIOM_MASK, pinmux) + +/** + * @brief Utility macro to initialize pinmux field in #pinctrl_pin_t. + * @param node_id Node identifier. + */ +#define Z_PINCTRL_CAT1_PINMUX_INIT(node_id) DT_PROP(node_id, pinmux) + +/** + * @brief Utility macro to initialize pincfg field in #pinctrl_pin_t. + * @param node_id Node identifier. + */ +#define Z_PINCTRL_CAT1_PINCFG_INIT(node_id) ( \ + (DT_PROP(node_id, bias_pull_up) << SOC_GPIO_PULLUP_POS) | \ + (DT_PROP(node_id, bias_pull_down) << SOC_GPIO_PULLDOWN_POS) | \ + (DT_PROP(node_id, drive_open_drain) << SOC_GPIO_OPENDRAIN_POS) | \ + (DT_PROP(node_id, drive_open_source) << SOC_GPIO_OPENSOURCE_POS) | \ + (DT_PROP(node_id, drive_push_pull) << SOC_GPIO_PUSHPULL_POS) | \ + (DT_PROP(node_id, input_enable) << SOC_GPIO_INPUTENABLE_POS) | \ + (DT_PROP(node_id, bias_high_impedance) << SOC_GPIO_HIGHZ_POS)) + +/** + * @brief Utility macro to initialize each pin. + * + * @param node_id Node identifier. + * @param state_prop State property name. + * @param idx State property entry index. + */ +#define Z_PINCTRL_STATE_PIN_INIT(node_id, state_prop, idx) \ + { .pinmux = Z_PINCTRL_CAT1_PINMUX_INIT( \ + DT_PROP_BY_IDX(node_id, state_prop, idx)), \ + .pincfg = Z_PINCTRL_CAT1_PINCFG_INIT( \ + DT_PROP_BY_IDX(node_id, state_prop, idx)) }, + +/** + * @brief Utility macro to initialize state pins contained in a given property. + * + * @param node_id Node identifier. + * @param prop Property name describing state pins. + */ +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + { DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT) } + +/** @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_SOC_ARM_INFINEON_CAT1_COMMON_PINCTRL_SOC_H_ */ diff --git a/soc/infineon/cat1a/psoc6_legacy/soc.h b/soc/infineon/cat1a/psoc6_legacy/soc.h index 8bd23b04ec2..a686d7a1b40 100644 --- a/soc/infineon/cat1a/psoc6_legacy/soc.h +++ b/soc/infineon/cat1a/psoc6_legacy/soc.h @@ -20,7 +20,6 @@ #ifndef _ASMLANGUAGE #include -#include "soc_gpio.h" #include "cypress_psoc6_dt.h" #endif /* !_ASMLANGUAGE */ diff --git a/soc/infineon/cat1a/psoc6_legacy/soc_gpio.c b/soc/infineon/cat1a/psoc6_legacy/soc_gpio.c deleted file mode 100644 index b58a88b0654..00000000000 --- a/soc/infineon/cat1a/psoc6_legacy/soc_gpio.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2016 Piotr Mienkowski - * Copyright (c) 2021 ATL Electronics - * SPDX-License-Identifier: Apache-2.0 - */ - -/** @file - * @brief Cypress PSoC-6 MCU family General Purpose Input Output (GPIO) - * module HAL driver. - */ - -#include "soc_gpio.h" -#include "cy_gpio.h" - -static uint32_t soc_gpio_get_drv_mode(uint32_t flags) -{ - uint32_t drv_mode = CY_GPIO_DM_ANALOG; - - flags = ((flags & SOC_GPIO_FLAGS_MASK) >> SOC_GPIO_FLAGS_POS); - - if (flags & SOC_GPIO_OPENDRAIN) { - drv_mode = CY_GPIO_DM_OD_DRIVESLOW_IN_OFF; - } else if (flags & SOC_GPIO_OPENSOURCE) { - drv_mode = CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF; - } else if (flags & SOC_GPIO_PUSHPULL) { - drv_mode = CY_GPIO_DM_STRONG_IN_OFF; - } else if ((flags & SOC_GPIO_PULLUP) && (flags & SOC_GPIO_PULLDOWN)) { - drv_mode = CY_GPIO_DM_PULLUP_DOWN_IN_OFF; - } else if (flags & SOC_GPIO_PULLUP) { - drv_mode = CY_GPIO_DM_PULLUP_IN_OFF; - } else if (flags & SOC_GPIO_PULLDOWN) { - drv_mode = CY_GPIO_DM_PULLDOWN_IN_OFF; - } else { - ; - } - - if (flags & SOC_GPIO_INPUTENABLE) { - drv_mode |= CY_GPIO_DM_HIGHZ; - } - - return drv_mode; -} - -void soc_gpio_configure(const struct soc_gpio_pin *pin) -{ - uint32_t drv_mode = soc_gpio_get_drv_mode(pin->flags); - uint32_t function = ((pin->flags & SOC_GPIO_FUNC_MASK) >> - SOC_GPIO_FUNC_POS); - - Cy_GPIO_SetHSIOM(pin->regs, pin->pinum, function); - Cy_GPIO_SetDrivemode(pin->regs, pin->pinum, drv_mode); -} - -void soc_gpio_list_configure(const struct soc_gpio_pin pins[], size_t size) -{ - for (size_t i = 0; i < size; i++) { - soc_gpio_configure(&pins[i]); - } -} diff --git a/soc/infineon/cat1a/psoc6_legacy/soc_gpio.h b/soc/infineon/cat1a/psoc6_legacy/soc_gpio.h deleted file mode 100644 index b14bcee4f72..00000000000 --- a/soc/infineon/cat1a/psoc6_legacy/soc_gpio.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2016-2017 Piotr Mienkowski - * Copyright (c) 2021 ATL Electronics - * SPDX-License-Identifier: Apache-2.0 - */ - -/** @file - * @brief Cypress PSoC-6 MCU family General Purpose Input Output (GPIO) - * module HAL driver. - */ - -#ifndef _CYPRESS_PSOC6_SOC_GPIO_H_ -#define _CYPRESS_PSOC6_SOC_GPIO_H_ - -#include -#include - -/* - * Pin flags/attributes - */ - -#define SOC_GPIO_DEFAULT (0) - -#define SOC_GPIO_FLAGS_POS (0) -#define SOC_GPIO_FLAGS_MASK (0x3F << SOC_GPIO_FLAGS_POS) -#define SOC_GPIO_PULLUP_POS (0) -#define SOC_GPIO_PULLUP (1 << SOC_GPIO_PULLUP_POS) -#define SOC_GPIO_PULLDOWN_POS (1) -#define SOC_GPIO_PULLDOWN (1 << SOC_GPIO_PULLDOWN_POS) -#define SOC_GPIO_OPENDRAIN_POS (2) -#define SOC_GPIO_OPENDRAIN (1 << SOC_GPIO_OPENDRAIN_POS) -#define SOC_GPIO_OPENSOURCE_POS (3) -#define SOC_GPIO_OPENSOURCE (1 << SOC_GPIO_OPENSOURCE_POS) -/* Push-Pull means Strong, see dts/pinctrl/pincfg-node.yaml */ -#define SOC_GPIO_PUSHPULL_POS (4) -#define SOC_GPIO_PUSHPULL (1 << SOC_GPIO_PUSHPULL_POS) -/* Input-Enable means Input-Buffer, see dts/pinctrl/pincfg-node.yaml */ -#define SOC_GPIO_INPUTENABLE_POS (5) -#define SOC_GPIO_INPUTENABLE (1 << SOC_GPIO_INPUTENABLE_POS) - -/* Bit field: SOC_GPIO_IN_FILTER */ -#define SOC_GPIO_IN_FILTER_POS (6) -#define SOC_GPIO_IN_FILTER_MASK (3 << SOC_GPIO_IN_FILTER_POS) -#define SOC_GPIO_IN_FILTER_NONE (0 << SOC_GPIO_IN_FILTER_POS) -#define SOC_GPIO_IN_FILTER_DEBOUNCE (1 << SOC_GPIO_IN_FILTER_POS) -#define SOC_GPIO_IN_FILTER_DEGLITCH (2 << SOC_GPIO_IN_FILTER_POS) - -#define SOC_GPIO_INT_ENABLE (1 << 8) - -/* Bit field: SOC_GPIO_INT_TRIG */ -#define SOC_GPIO_INT_TRIG_POS (9) -#define SOC_GPIO_INT_TRIG_MASK (3 << SOC_GPIO_INT_TRIG_POS) -/** Interrupt is triggered by a level detection event. */ -#define SOC_GPIO_INT_TRIG_LEVEL (0 << SOC_GPIO_INT_TRIG_POS) -/** Interrupt is triggered by an edge detection event. */ -#define SOC_GPIO_INT_TRIG_EDGE (1 << SOC_GPIO_INT_TRIG_POS) -/** Interrupt is triggered by any edge detection event. */ -#define SOC_GPIO_INT_TRIG_DOUBLE_EDGE (2 << SOC_GPIO_INT_TRIG_POS) - -/** Interrupt is triggered by a high level / rising edge detection event */ -#define SOC_GPIO_INT_ACTIVE_HIGH (1 << 11) - -/* Bit field: SOC_GPIO_FUNC */ -#define SOC_GPIO_FUNC_POS (16) -#define SOC_GPIO_FUNC_MASK (0x1F << SOC_GPIO_FUNC_POS) - -struct soc_gpio_pin { - GPIO_PRT_Type *regs; /** pointer to registers of the GPIO controller */ - uint32_t pinum; /** pin number */ - uint32_t flags; /** pin flags/attributes */ -}; - -/** - * @brief Configure GPIO pin(s). - * - * Configure one or several pins belonging to the same GPIO port. - * Example scenarios: - * - configure pin(s) as input with debounce filter enabled. - * - connect pin(s) to a HSIOM function and enable pull-up. - * - configure pin(s) as open drain output. - * All pins are configured in the same way. - * - * @param pin pin's configuration data such as pin mask, pin attributes, etc. - */ -void soc_gpio_configure(const struct soc_gpio_pin *pin); - -/** - * @brief Configure a list of GPIO pin(s). - * - * Configure an arbitrary amount of pins in an arbitrary way. Each - * configuration entry is a single item in an array passed as an - * argument to the function. - * - * @param pins an array where each item contains pin's configuration data. - * @param size size of the pin list. - */ -void soc_gpio_list_configure(const struct soc_gpio_pin pins[], size_t size); - -#endif /* _CYPRESS_PSOC6_SOC_GPIO_H_ */