soc: psoc6: update pinctrl for PSoC6 MCU (legacy)

update pinctrl for PSoC6 MCU (legacy)

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>

dts/bindings/pinctrl/cypress,psoc6-pinctrl.yaml

@@ -1,39 +0,0 @@
-# Copyright (c) 2020, Linaro Limited
-# Copyright (c) 2021, ATL Electronics
-# SPDX-License-Identifier: Apache-2.0
-
-description: |
-  Cypress PSoC-6 Pinctrl container node
-
-  The Cypress PSoC-6 pins implements following pin configuration option:
-
-    * bias-pull-up
-    * bias-pull-down
-    * drive-open-drain
-    * drive-open-source
-    * drive-push-pull   (strong)
-    * input-enable      (input-buffer)
-
-  These options define devicetree flags that are converted to SoC flags at
-  CY_PSOC6_PIN_FLAGS().
-
-compatible: "cypress,psoc6-pinctrl"
-
-include: base.yaml
-
-properties:
-  "#address-cells":
-    required: true
-    const: 1
-  "#size-cells":
-    required: true
-    const: 1
-
-child-binding:
-  description: cypress pins
-
-  include: pincfg-node.yaml
-
-  properties:
-    "cypress,pins":
-      type: phandle-array

dts/bindings/serial/cypress,psoc6-uart.yaml

@@ -6,7 +6,7 @@ description: Cypress SCB[UART]
 
 compatible: "cypress,psoc6-uart"
 
-include: uart-controller.yaml
+include: [uart-controller.yaml, pinctrl-device.yaml]
 
 properties:
   reg:

dts/bindings/spi/cypress,psoc6-spi.yaml

@@ -5,7 +5,7 @@ description: Cypress SBC[SPI]
 
 compatible: "cypress,psoc6-spi"
 
-include: spi-controller.yaml
+include: [spi-controller.yaml, pinctrl-device.yaml]
 
 properties:
   reg: