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soc: psoc6: update pinctrl for PSoC6 MCU (legacy)

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update pinctrl for PSoC6 MCU (legacy)

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
This commit is contained in:
Nazar Palamar 2024-05-14 11:37:43 +03:00 • committed by Alberto Escolar
commit 7c3b66eac8
23 changed files with 972 additions and 359 deletions
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5
boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_common.dtsi
View file

@ -86,7 +86,8 @@
&spi6 {
cs-gpios = <&gpio_prt12 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>,
<&gpio_prt13 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
<&gpio_prt13 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
pinctrl-0 = <&p12_0_spi6_mosi &p12_1_spi6_miso &p12_2_spi6_clk>;
pinctrl-0 = <&p12_0_scb6_spi_m_mosi &p12_1_scb6_spi_m_miso &p12_2_scb6_spi_m_clk>;
pinctrl-names = "default";
};

45
boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347-pinctrl.dtsi Normal file
View file

@ -0,0 +1,45 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#include <infineon/cat1a/legacy/psoc6-pinctrl.dtsi>
/* Configure pin control bias mode for uart5 pins */
&p5_1_scb5_uart_tx {
drive-push-pull;
};
&p5_0_scb5_uart_rx {
input-enable;
};
&p9_1_scb2_uart_tx {
drive-push-pull;
};
&p9_0_scb2_uart_rx {
input-enable;
};
&p13_1_scb6_uart_tx {
drive-push-pull;
};
&p13_0_scb6_uart_rx {
input-enable;
};
/* Configure pin control bias mode for SPI pins */
&p12_0_scb6_spi_m_mosi {
drive-push-pull;
};
&p12_1_scb6_spi_m_miso {
input-enable;
};
&p12_2_scb6_spi_m_clk {
drive-push-pull;
};

4
boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.overlay
View file

@ -3,6 +3,7 @@
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "cy8ckit_062_ble_cy8c6347-pinctrl.dtsi"
/ {
aliases {
@ -21,7 +22,8 @@
interrupt-parent = <&intmux_ch21>;
pinctrl-0 = <&p5_0_uart5_rx &p5_1_uart5_tx>;
pinctrl-0 = <&p5_0_scb5_uart_rx &p5_1_scb5_uart_tx>;
pinctrl-names = "default";
};
arduino_serial: &uart5 {};

10
boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.overlay
View file

@ -4,6 +4,8 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "cy8ckit_062_ble_cy8c6347-pinctrl.dtsi"
/ {
aliases {
uart-2 = &uart2;
@ -21,7 +23,9 @@
interrupt-parent = <&intmux_ch21>;
pinctrl-0 = <&p9_0_uart2_rx &p9_1_uart2_tx>;
pinctrl-0 = <&p9_0_scb2_uart_rx &p9_1_scb2_uart_tx>;
pinctrl-names = "default";
};
&uart5 {
@ -30,7 +34,9 @@
interrupt-parent = <&intmux_ch22>;
pinctrl-0 = <&p5_0_uart5_rx &p5_1_uart5_tx>;
pinctrl-0 = <&p5_0_scb5_uart_rx &p5_1_scb5_uart_tx>;
pinctrl-names = "default";
};
arduino_serial: &uart5 {};

5
boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.overlay
View file

@ -4,6 +4,8 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "cy8ckit_062_ble_cy8c6347-pinctrl.dtsi"
/ {
aliases {
uart-6 = &uart6;
@ -19,5 +21,6 @@
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&p13_0_uart6_rx &p13_1_uart6_tx>;
pinctrl-0 = <&p13_0_scb6_uart_rx &p13_1_scb6_uart_tx>;
pinctrl-names = "default";
};

45
boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247-pinctrl.dtsi Normal file
View file

@ -0,0 +1,45 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#include <infineon/cat1a/legacy/psoc6-pinctrl.dtsi>
/* Configure pin control bias mode for uart5 pins */
&p5_1_scb5_uart_tx {
drive-push-pull;
};
&p5_0_scb5_uart_rx {
input-enable;
};
&p9_1_scb2_uart_tx {
drive-push-pull;
};
&p9_0_scb2_uart_rx {
input-enable;
};
&p13_1_scb6_uart_tx {
drive-push-pull;
};
&p13_0_scb6_uart_rx {
input-enable;
};
/* Configure pin control bias mode for SPI pins */
&p12_0_scb6_spi_m_mosi {
drive-push-pull;
};
&p12_1_scb6_spi_m_miso {
input-enable;
};
&p12_2_scb6_spi_m_clk {
drive-push-pull;
};

4
boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.dts
View file

@ -9,6 +9,7 @@
#include <infineon/cat1a/legacy/psoc6_cm0.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include "cy8ckit_062_wifi_bt_cy8c6247-pinctrl.dtsi"
/ {
model = "cy8ckit_062_wifi_bt_m0 with a Cypress PSoC6 SoC";
@ -61,5 +62,6 @@
interrupt-parent = <&intmux_ch21>;
pinctrl-0 = <&p13_0_uart6_rx &p13_1_uart6_tx>;
pinctrl-0 = <&p13_0_scb6_uart_rx &p13_1_scb6_uart_tx>;
pinctrl-names = "default";
};

4
boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.dts
View file

@ -7,6 +7,7 @@
/dts-v1/;
#include <infineon/cat1a/legacy/psoc6_cm4.dtsi>
#include "cy8ckit_062_wifi_bt_cy8c6247-pinctrl.dtsi"
/ {
model = "cy8ckit_062_wifi_bt_m4 with a Cypress PSoC6 SoC";
@ -28,5 +29,6 @@
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&p5_0_uart5_rx &p5_1_uart5_tx>;
pinctrl-0 = <&p5_0_scb5_uart_rx &p5_1_scb5_uart_tx>;
pinctrl-names = "default";
};