drivers: pinctrl: Add support for RZ/V2L
This is the initial commit to support pinctrl driver for Renesas RZ/V2L Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com> Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com> Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
This commit is contained in:
Quang Le
Benjamin Cabé
parent
62a721f1fd
commit
7c27e576a0
7 changed files with 378 additions and 2 deletions
16
boards/renesas/rzv2l_smarc/rzv2l_smarc-pinctrl.dtsi
Normal file
16
boards/renesas/rzv2l_smarc/rzv2l_smarc-pinctrl.dtsi
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@ -0,0 +1,16 @@
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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzv-common.h>
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&pinctrl {
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/omit-if-no-ref/ scif2_pins: scif2 {
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scif2-pinmux {
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pinmux = <RZV_PINMUX(PORT_48, 0, 1)>, /* TXD */
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<RZV_PINMUX(PORT_48, 1, 1)>; /* RXD */
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};
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};
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};
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@ -1,5 +1,5 @@
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# Copyright (c) 2023 Antmicro <www.antmicro.com>
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# Copyright (c) 2023 Antmicro <www.antmicro.com>
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# Copyright (c) 2024 Renesas Electronics Corporation
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# Copyright (c) 2024-2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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# SPDX-License-Identifier: Apache-2.0
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config PINCTRL_RZT2M
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config PINCTRL_RZT2M
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@ -15,7 +15,8 @@ config PINCTRL_RENESAS_RZ
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depends on DT_HAS_RENESAS_RZG_PINCTRL_ENABLED \
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depends on DT_HAS_RENESAS_RZG_PINCTRL_ENABLED \
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|| DT_HAS_RENESAS_RZN_PINCTRL_ENABLED \
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|| DT_HAS_RENESAS_RZN_PINCTRL_ENABLED \
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|| DT_HAS_RENESAS_RZT_PINCTRL_ENABLED \
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|| DT_HAS_RENESAS_RZT_PINCTRL_ENABLED \
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|| DT_HAS_RENESAS_RZA_PINCTRL_ENABLED
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|| DT_HAS_RENESAS_RZA_PINCTRL_ENABLED \
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|| DT_HAS_RENESAS_RZV_PINCTRL_ENABLED
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select USE_RZ_FSP_IOPORT
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select USE_RZ_FSP_IOPORT
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help
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help
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Enable Renesas RZ pinctrl driver.
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Enable Renesas RZ pinctrl driver.
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@ -32,6 +32,12 @@
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};
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};
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soc {
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soc {
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pinctrl: pin-controller@41030000 {
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compatible = "renesas,rzv-pinctrl";
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reg = <0x41030000 DT_SIZE_K(64)>;
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reg-names = "pinctrl";
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};
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scif0: serial@4004b800 {
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scif0: serial@4004b800 {
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compatible = "renesas,rz-scif-uart";
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compatible = "renesas,rz-scif-uart";
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channel = <0>;
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channel = <0>;
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101
dts/bindings/pinctrl/renesas,rzv-pinctrl.yaml
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101
dts/bindings/pinctrl/renesas,rzv-pinctrl.yaml
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@ -0,0 +1,101 @@
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# Copyright (c) 2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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description: |
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Renesas RZ/V pin controller
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The Renesas RZ/V pin controller is a node responsible for controlling
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pin function selection and pin properties, such as routing the TX and RX of UART2
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to pin 0 and pin 1 of port 48.
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#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzv-common.h>
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example_pins: device_pin {
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device-pinmux {
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pinmux = <RZV_PINMUX(PORT_04, 0, 2)>,
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<RZV_PINMUX(PORT_04, 1, 2);
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bias_pull_up;
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renesas,filter = RZV_FILTER_SET(RZV_FILNUM_8_STAGE,RZV_FILCLKSEL_DIV_18000);
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drive-strength = <1>;
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slew-rate = <fast>;
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};
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device-spins {
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pins = <BSP_IO_QSPI0_IO0>, <BSP_IO_QSPI0_IO3>;
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input-enable;
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renesas,filter = RZV_FILTER_SET(RZV_FILNUM_8_STAGE,RZV_FILCLKSEL_DIV_18000);
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drive-strength = <2>;
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slew-rate = "fast";
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};
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};
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compatible: renesas,rzv-pinctrl
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include: base.yaml
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properties:
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reg:
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required: true
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reg-names:
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required: true
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child-binding:
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description: |
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This RZV pins mux/cfg nodes description.
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child-binding:
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description: |
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The RZV pinmux/pincfg configuration nodes description.
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include:
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- name: pincfg-node.yaml
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property-allowlist:
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- bias-pull-down
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- bias-pull-up
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- drive-strength
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- input-enable
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properties:
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pinmux:
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type: array
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description: |
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Pinmux configuration node.
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Values are constructed from GPIO port number, pin number, and
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alternate function configuration number using the RZV_PINMUX()
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helper macro in pinctrl-rzv-common.h
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pins:
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type: array
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description: |
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Special Purpose pins configuration node.
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Values are define in pinctrl-rzv-common.h.
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Ex: BSP_IO_QSPI0_IO0,BSP_IO_RIIC1_SCL,...
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drive-strength:
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type: int
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default: 0
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description: |
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Maximum sink or source current in mA for pin which shell be selected
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depending on device and pin group.
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renesas,filter:
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type: int
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default: 0
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description: |
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Digital Noise Filter configuration for a pin which shell be defined
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using RZV_FILTER_SET() helper macro in pinctrl-rzv-common.h to specify
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FILNUM and FILCLKSEL. With 24Mhz external clock:
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- min debounce time will be 166.666ns for FILNUM=0 and FILCLKSEL=0
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- max debounce time will be 24ms for FILNUM=3 and FILCLKSEL=3.
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This property intentionally redefined to avoid unnecessary conversation from usec to
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FILNUM and FILCLKSEL values depending on external clock value as this configuration
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is static.
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slew-rate:
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type: string
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default: "fast"
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enum:
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- "slow"
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- "fast"
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description: |
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Select slew rate for pin.
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139
include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzv-common.h
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139
include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzv-common.h
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@ -0,0 +1,139 @@
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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZV_COMMON_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZV_COMMON_H_
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/* Superset list of all possible IO ports. */
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#define PORT_00 0x0000 /* IO port 0 */
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#define PORT_01 0x0100 /* IO port 1 */
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#define PORT_02 0x0200 /* IO port 2 */
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#define PORT_03 0x0300 /* IO port 3 */
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#define PORT_04 0x0400 /* IO port 4 */
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#define PORT_05 0x0500 /* IO port 5 */
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#define PORT_06 0x0600 /* IO port 6 */
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#define PORT_07 0x0700 /* IO port 7 */
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#define PORT_08 0x0800 /* IO port 8 */
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#define PORT_09 0x0900 /* IO port 9 */
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#define PORT_10 0x0A00 /* IO port 10 */
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#define PORT_11 0x0B00 /* IO port 11 */
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#define PORT_12 0x0C00 /* IO port 12 */
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#define PORT_13 0x0D00 /* IO port 13 */
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#define PORT_14 0x0E00 /* IO port 14 */
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#define PORT_15 0x0F00 /* IO port 15 */
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#define PORT_16 0x1000 /* IO port 16 */
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#define PORT_17 0x1100 /* IO port 17 */
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#define PORT_18 0x1200 /* IO port 18 */
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#define PORT_19 0x1300 /* IO port 19 */
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#define PORT_20 0x1400 /* IO port 20 */
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#define PORT_21 0x1500 /* IO port 21 */
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#define PORT_22 0x1600 /* IO port 22 */
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#define PORT_23 0x1700 /* IO port 23 */
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#define PORT_24 0x1800 /* IO port 24 */
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#define PORT_25 0x1900 /* IO port 25 */
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#define PORT_26 0x1A00 /* IO port 26 */
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#define PORT_27 0x1B00 /* IO port 27 */
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#define PORT_28 0x1C00 /* IO port 28 */
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#define PORT_29 0x1D00 /* IO port 29 */
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#define PORT_30 0x1E00 /* IO port 30 */
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#define PORT_31 0x1F00 /* IO port 31 */
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#define PORT_32 0x2000 /* IO port 32 */
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#define PORT_33 0x2100 /* IO port 33 */
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#define PORT_34 0x2200 /* IO port 34 */
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#define PORT_35 0x2300 /* IO port 35 */
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#define PORT_36 0x2400 /* IO port 36 */
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#define PORT_37 0x2500 /* IO port 37 */
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#define PORT_38 0x2600 /* IO port 38 */
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#define PORT_39 0x2700 /* IO port 39 */
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#define PORT_40 0x2800 /* IO port 40 */
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#define PORT_41 0x2900 /* IO port 41 */
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#define PORT_42 0x2A00 /* IO port 42 */
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#define PORT_43 0x2B00 /* IO port 43 */
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#define PORT_44 0x2C00 /* IO port 44 */
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#define PORT_45 0x2D00 /* IO port 45 */
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#define PORT_46 0x2E00 /* IO port 46 */
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#define PORT_47 0x2F00 /* IO port 47 */
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#define PORT_48 0x3000 /* IO port 48 */
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/*
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* Create the value contain port/pin/function information
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*
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* port: port number BSP_IO_PORT_00..BSP_IO_PORT_48
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* pin: pin number
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* func: pin function
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*/
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#define RZV_PINMUX(port, pin, func) (port | pin | (func << 4))
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/* Special purpose port */
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#define BSP_IO_NMI 0xFFFF0100 /* NMI */
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#define BSP_IO_TMS_SWDIO 0xFFFF0200 /* TMS_SWDIO */
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#define BSP_IO_TDO 0xFFFF0300 /* TDO */
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#define BSP_IO_AUDIO_CLK1 0xFFFF0400 /* AUDIO_CLK1 */
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#define BSP_IO_AUDIO_CLK2 0xFFFF0401 /* AUDIO_CLK2 */
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#define BSP_IO_SD0_CLK 0xFFFF0600 /* SD0_CLK */
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#define BSP_IO_SD0_CMD 0xFFFF0601 /* SD0_CMD */
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#define BSP_IO_SD0_RST_N 0xFFFF0602 /* SD0_RST_N */
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#define BSP_IO_SD0_DATA0 0xFFFF0700 /* SD0_DATA0 */
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#define BSP_IO_SD0_DATA1 0xFFFF0701 /* SD0_DATA1 */
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#define BSP_IO_SD0_DATA2 0xFFFF0702 /* SD0_DATA2 */
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#define BSP_IO_SD0_DATA3 0xFFFF0703 /* SD0_DATA3 */
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#define BSP_IO_SD0_DATA4 0xFFFF0704 /* SD0_DATA4 */
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#define BSP_IO_SD0_DATA5 0xFFFF0705 /* SD0_DATA5 */
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#define BSP_IO_SD0_DATA6 0xFFFF0706 /* SD0_DATA6 */
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#define BSP_IO_SD0_DATA7 0xFFFF0707 /* SD0_DATA7 */
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#define BSP_IO_SD1_CLK 0xFFFF0800 /* SD1_CLK */
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#define BSP_IO_SD1_CMD 0xFFFF0801 /* SD1_CMD */
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#define BSP_IO_SD1_DATA0 0xFFFF0900 /* SD1_DATA0 */
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#define BSP_IO_SD1_DATA1 0xFFFF0901 /* SD1_DATA1 */
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#define BSP_IO_SD1_DATA2 0xFFFF0902 /* SD1_DATA2 */
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#define BSP_IO_SD1_DATA3 0xFFFF0903 /* SD1_DATA3 */
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#define BSP_IO_QSPI0_SPCLK 0xFFFF0A00 /* QSPI0_SPCLK */
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#define BSP_IO_QSPI0_IO0 0xFFFF0A01 /* QSPI0_IO0 */
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#define BSP_IO_QSPI0_IO1 0xFFFF0A02 /* QSPI0_IO1 */
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#define BSP_IO_QSPI0_IO2 0xFFFF0A03 /* QSPI0_IO2 */
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#define BSP_IO_QSPI0_IO3 0xFFFF0A04 /* QSPI0_IO3 */
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#define BSP_IO_QSPI0_SSL 0xFFFF0A05 /* QSPI0_SSL */
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#define BSP_IO_QSPI1_SPCLK 0xFFFF0B00 /* QSPI1_SPCLK */
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#define BSP_IO_QSPI1_IO0 0xFFFF0B01 /* QSPI1_IO0 */
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#define BSP_IO_QSPI1_IO1 0xFFFF0B02 /* QSPI1_IO1 */
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#define BSP_IO_QSPI1_IO2 0xFFFF0B03 /* QSPI1_IO2 */
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#define BSP_IO_QSPI1_IO3 0xFFFF0B04 /* QSPI1_IO3 */
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#define BSP_IO_QSPI1_SSL 0xFFFF0B05 /* QSPI1_SSL */
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#define BSP_IO_QSPI_RESET_N 0xFFFF0C00 /* QSPI_RESET_N */
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#define BSP_IO_QSPI_WP_N 0xFFFF0C01 /* QSPI_WP_N */
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#define BSP_IO_QSPI_INT_N 0xFFFF0C02 /* QSPI_INT_N */
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#define BSP_IO_WDTOVF_PERROUT_N 0xFFFF0D00 /* WDTOVF_PERROUT_N */
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#define BSP_IO_RIIC0_SDA 0xFFFF0E00 /* RIIC0_SDA */
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#define BSP_IO_RIIC0_SCL 0xFFFF0E01 /* RIIC0_SCL */
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#define BSP_IO_RIIC1_SDA 0xFFFF0E02 /* RIIC1_SDA */
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#define BSP_IO_RIIC1_SCL 0xFFFF0E03 /* RIIC1_SCL */
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/* FILNUM */
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#define RZV_FILNUM_4_STAGE 0
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#define RZV_FILNUM_8_STAGE 1
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#define RZV_FILNUM_12_STAGE 2
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#define RZV_FILNUM_16_STAGE 3
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/* FILCLKSEL */
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#define RZV_FILCLKSEL_NOT_DIV 0
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#define RZV_FILCLKSEL_DIV_9000 1
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#define RZV_FILCLKSEL_DIV_18000 2
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#define RZV_FILCLKSEL_DIV_36000 3
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#define RZV_FILTER_SET(filnum, filclksel) (((filnum) & 0x3) << 0x2) | (filclksel & 0x3)
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZV_COMMON_H_ */
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102
soc/renesas/rz/common/pinctrl_rzv.h
Normal file
102
soc/renesas/rz/common/pinctrl_rzv.h
Normal file
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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZV_H_
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#define ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZV_H_
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#include <zephyr/devicetree.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/types.h>
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#include "r_ioport.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Porting */
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typedef struct pinctrl_cfg_data_t {
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uint32_t reserved: 4;
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uint32_t pupd_reg: 6;
|
||||||
|
uint32_t iolh_reg: 6;
|
||||||
|
uint32_t pmc_reg: 1;
|
||||||
|
uint32_t sr_reg: 1;
|
||||||
|
uint32_t ien_reg: 1;
|
||||||
|
uint32_t filonoff_reg: 1;
|
||||||
|
uint32_t filnum_reg: 2;
|
||||||
|
uint32_t filclksel_reg: 2;
|
||||||
|
uint32_t pfc_reg: 3;
|
||||||
|
} pinctrl_cfg_data_t;
|
||||||
|
|
||||||
|
typedef struct pinctrl_soc_pin_t {
|
||||||
|
bsp_io_port_pin_t port_pin;
|
||||||
|
pinctrl_cfg_data_t config;
|
||||||
|
} pinctrl_soc_pin_t;
|
||||||
|
|
||||||
|
/* Iterate over each pinctrl-n phandle child */
|
||||||
|
#define Z_PINCTRL_STATE_PIN_INIT(node_id, state_prop, idx) \
|
||||||
|
DT_FOREACH_CHILD(DT_PHANDLE_BY_IDX(node_id, state_prop, idx), \
|
||||||
|
Z_PINCTRL_STATE_PIN_CHILD_INIT)
|
||||||
|
|
||||||
|
/* Iterate over each pinctrl-n phandle child */
|
||||||
|
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
|
||||||
|
{DT_FOREACH_PROP_ELEM_SEP(node_id, prop, Z_PINCTRL_STATE_PIN_INIT, ())};
|
||||||
|
|
||||||
|
#define Z_PINCTRL_STATE_PIN_CHILD_INIT(node_id) \
|
||||||
|
COND_CODE_1(DT_NODE_HAS_PROP(node_id, pinmux), \
|
||||||
|
(DT_FOREACH_PROP_ELEM(node_id, pinmux, Z_PINCTRL_PINMUX_INIT)), \
|
||||||
|
()) \
|
||||||
|
COND_CODE_1(DT_NODE_HAS_PROP(node_id, pins), \
|
||||||
|
(DT_FOREACH_PROP_ELEM(node_id, pins, Z_PINCTRL_SPECIAL_PINS_INIT)), \
|
||||||
|
())
|
||||||
|
|
||||||
|
#define RZV_GET_PORT_PIN(pinmux) (pinmux & ~(0xF << 4))
|
||||||
|
#define RZV_GET_FUNC(pinmux) ((pinmux & 0xF0) >> 4)
|
||||||
|
|
||||||
|
#define RZV_GET_PU_PD(node_id) \
|
||||||
|
DT_PROP(node_id, bias_pull_up) == 1 ? 1U : (DT_PROP(node_id, bias_pull_down) == 1 ? 2U : 0U)
|
||||||
|
|
||||||
|
#define RZV_GET_FILNUM(node_id) ((DT_PROP(node_id, renesas_filter) >> 2) & 0x3)
|
||||||
|
|
||||||
|
#define RZV_GET_FILCLKSEL(node_id) (DT_PROP(node_id, renesas_filter) & 0x3)
|
||||||
|
|
||||||
|
#define RZV_FILTER_ON_OFF(node_id) COND_CODE_0(DT_PROP(node_id, renesas_filter), (0), (1))
|
||||||
|
|
||||||
|
/* Process pinmux cfg */
|
||||||
|
#define Z_PINCTRL_PINMUX_INIT(node_id, state_prop, idx) \
|
||||||
|
{ \
|
||||||
|
.port_pin = RZV_GET_PORT_PIN(DT_PROP_BY_IDX(node_id, state_prop, idx)), \
|
||||||
|
.config = {.reserved = 0, \
|
||||||
|
.pupd_reg = RZV_GET_PU_PD(node_id), \
|
||||||
|
.iolh_reg = DT_PROP(node_id, drive_strength), \
|
||||||
|
.pmc_reg = 1, \
|
||||||
|
.sr_reg = DT_ENUM_IDX(node_id, slew_rate), \
|
||||||
|
.ien_reg = DT_PROP(node_id, input_enable), \
|
||||||
|
.filonoff_reg = RZV_FILTER_ON_OFF(node_id), \
|
||||||
|
.filnum_reg = RZV_GET_FILNUM(node_id), \
|
||||||
|
.filclksel_reg = RZV_GET_FILCLKSEL(node_id), \
|
||||||
|
.pfc_reg = RZV_GET_FUNC(DT_PROP_BY_IDX(node_id, state_prop, idx))}, \
|
||||||
|
},
|
||||||
|
|
||||||
|
#define Z_PINCTRL_SPECIAL_PINS_INIT(node_id, state_prop, idx) \
|
||||||
|
{ \
|
||||||
|
.port_pin = DT_PROP_BY_IDX(node_id, state_prop, idx), \
|
||||||
|
.config = \
|
||||||
|
{ \
|
||||||
|
.reserved = 0, \
|
||||||
|
.pupd_reg = RZV_GET_PU_PD(node_id), \
|
||||||
|
.iolh_reg = DT_PROP(node_id, drive_strength), \
|
||||||
|
.pmc_reg = 0, \
|
||||||
|
.sr_reg = DT_ENUM_IDX(node_id, slew_rate), \
|
||||||
|
.ien_reg = DT_PROP(node_id, input_enable), \
|
||||||
|
.filonoff_reg = RZV_FILTER_ON_OFF(node_id), \
|
||||||
|
.filnum_reg = RZV_GET_FILNUM(node_id), \
|
||||||
|
.filclksel_reg = RZV_GET_FILCLKSEL(node_id), \
|
||||||
|
.pfc_reg = 0, \
|
||||||
|
}, \
|
||||||
|
},
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#endif /* ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZV_H_ */
|
||||||
11
soc/renesas/rz/rzv2l/pinctrl_soc.h
Normal file
11
soc/renesas/rz/rzv2l/pinctrl_soc.h
Normal file
|
|
@ -0,0 +1,11 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2025 Renesas Electronics Corporation
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef ZEPHYR_SOC_RENESAS_RZ_RZV2L_PINCTRL_SOC_H_
|
||||||
|
#define ZEPHYR_SOC_RENESAS_RZ_RZV2L_PINCTRL_SOC_H_
|
||||||
|
|
||||||
|
#include <pinctrl_rzv.h>
|
||||||
|
|
||||||
|
#endif /* ZEPHYR_SOC_RENESAS_RZ_RZV2L_PINCTRL_SOC_H_ */
|
||||||
Loading…
Add table
Add a link
Reference in a new issue