diff --git a/boards/renesas/rzv2l_smarc/rzv2l_smarc-pinctrl.dtsi b/boards/renesas/rzv2l_smarc/rzv2l_smarc-pinctrl.dtsi new file mode 100644 index 00000000000..3795c701c8f --- /dev/null +++ b/boards/renesas/rzv2l_smarc/rzv2l_smarc-pinctrl.dtsi @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +&pinctrl { + /omit-if-no-ref/ scif2_pins: scif2 { + scif2-pinmux { + pinmux = , /* TXD */ + ; /* RXD */ + }; + }; +}; diff --git a/drivers/pinctrl/renesas/rz/Kconfig b/drivers/pinctrl/renesas/rz/Kconfig index f43b898948f..42fa2b4d7c5 100644 --- a/drivers/pinctrl/renesas/rz/Kconfig +++ b/drivers/pinctrl/renesas/rz/Kconfig @@ -1,5 +1,5 @@ # Copyright (c) 2023 Antmicro -# Copyright (c) 2024 Renesas Electronics Corporation +# Copyright (c) 2024-2025 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 config PINCTRL_RZT2M @@ -15,7 +15,8 @@ config PINCTRL_RENESAS_RZ depends on DT_HAS_RENESAS_RZG_PINCTRL_ENABLED \ || DT_HAS_RENESAS_RZN_PINCTRL_ENABLED \ || DT_HAS_RENESAS_RZT_PINCTRL_ENABLED \ - || DT_HAS_RENESAS_RZA_PINCTRL_ENABLED + || DT_HAS_RENESAS_RZA_PINCTRL_ENABLED \ + || DT_HAS_RENESAS_RZV_PINCTRL_ENABLED select USE_RZ_FSP_IOPORT help Enable Renesas RZ pinctrl driver. diff --git a/dts/arm/renesas/rz/rzv/r9a07g054.dtsi b/dts/arm/renesas/rz/rzv/r9a07g054.dtsi index aa2f49ce32a..8227ff235f9 100644 --- a/dts/arm/renesas/rz/rzv/r9a07g054.dtsi +++ b/dts/arm/renesas/rz/rzv/r9a07g054.dtsi @@ -32,6 +32,12 @@ }; soc { + pinctrl: pin-controller@41030000 { + compatible = "renesas,rzv-pinctrl"; + reg = <0x41030000 DT_SIZE_K(64)>; + reg-names = "pinctrl"; + }; + scif0: serial@4004b800 { compatible = "renesas,rz-scif-uart"; channel = <0>; diff --git a/dts/bindings/pinctrl/renesas,rzv-pinctrl.yaml b/dts/bindings/pinctrl/renesas,rzv-pinctrl.yaml new file mode 100644 index 00000000000..acf28285029 --- /dev/null +++ b/dts/bindings/pinctrl/renesas,rzv-pinctrl.yaml @@ -0,0 +1,101 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: | + Renesas RZ/V pin controller + + The Renesas RZ/V pin controller is a node responsible for controlling + pin function selection and pin properties, such as routing the TX and RX of UART2 + to pin 0 and pin 1 of port 48. + + #include + example_pins: device_pin { + device-pinmux { + pinmux = , + ; + slew-rate = ; + }; + + device-spins { + pins = , ; + input-enable; + renesas,filter = RZV_FILTER_SET(RZV_FILNUM_8_STAGE,RZV_FILCLKSEL_DIV_18000); + drive-strength = <2>; + slew-rate = "fast"; + }; + }; + + +compatible: renesas,rzv-pinctrl + +include: base.yaml +properties: + reg: + required: true + + reg-names: + required: true + +child-binding: + description: | + This RZV pins mux/cfg nodes description. + + child-binding: + description: | + The RZV pinmux/pincfg configuration nodes description. + + include: + - name: pincfg-node.yaml + property-allowlist: + - bias-pull-down + - bias-pull-up + - drive-strength + - input-enable + + properties: + pinmux: + type: array + description: | + Pinmux configuration node. + Values are constructed from GPIO port number, pin number, and + alternate function configuration number using the RZV_PINMUX() + helper macro in pinctrl-rzv-common.h + + pins: + type: array + description: | + Special Purpose pins configuration node. + Values are define in pinctrl-rzv-common.h. + Ex: BSP_IO_QSPI0_IO0,BSP_IO_RIIC1_SCL,... + + drive-strength: + type: int + default: 0 + description: | + Maximum sink or source current in mA for pin which shell be selected + depending on device and pin group. + + renesas,filter: + type: int + default: 0 + description: | + Digital Noise Filter configuration for a pin which shell be defined + using RZV_FILTER_SET() helper macro in pinctrl-rzv-common.h to specify + FILNUM and FILCLKSEL. With 24Mhz external clock: + - min debounce time will be 166.666ns for FILNUM=0 and FILCLKSEL=0 + - max debounce time will be 24ms for FILNUM=3 and FILCLKSEL=3. + This property intentionally redefined to avoid unnecessary conversation from usec to + FILNUM and FILCLKSEL values depending on external clock value as this configuration + is static. + + slew-rate: + type: string + default: "fast" + enum: + - "slow" + - "fast" + description: | + Select slew rate for pin. diff --git a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzv-common.h b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzv-common.h new file mode 100644 index 00000000000..2d2ae8f32b9 --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzv-common.h @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZV_COMMON_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZV_COMMON_H_ + +/* Superset list of all possible IO ports. */ +#define PORT_00 0x0000 /* IO port 0 */ +#define PORT_01 0x0100 /* IO port 1 */ +#define PORT_02 0x0200 /* IO port 2 */ +#define PORT_03 0x0300 /* IO port 3 */ +#define PORT_04 0x0400 /* IO port 4 */ +#define PORT_05 0x0500 /* IO port 5 */ +#define PORT_06 0x0600 /* IO port 6 */ +#define PORT_07 0x0700 /* IO port 7 */ +#define PORT_08 0x0800 /* IO port 8 */ +#define PORT_09 0x0900 /* IO port 9 */ +#define PORT_10 0x0A00 /* IO port 10 */ +#define PORT_11 0x0B00 /* IO port 11 */ +#define PORT_12 0x0C00 /* IO port 12 */ +#define PORT_13 0x0D00 /* IO port 13 */ +#define PORT_14 0x0E00 /* IO port 14 */ +#define PORT_15 0x0F00 /* IO port 15 */ +#define PORT_16 0x1000 /* IO port 16 */ +#define PORT_17 0x1100 /* IO port 17 */ +#define PORT_18 0x1200 /* IO port 18 */ +#define PORT_19 0x1300 /* IO port 19 */ +#define PORT_20 0x1400 /* IO port 20 */ +#define PORT_21 0x1500 /* IO port 21 */ +#define PORT_22 0x1600 /* IO port 22 */ +#define PORT_23 0x1700 /* IO port 23 */ +#define PORT_24 0x1800 /* IO port 24 */ +#define PORT_25 0x1900 /* IO port 25 */ +#define PORT_26 0x1A00 /* IO port 26 */ +#define PORT_27 0x1B00 /* IO port 27 */ +#define PORT_28 0x1C00 /* IO port 28 */ +#define PORT_29 0x1D00 /* IO port 29 */ +#define PORT_30 0x1E00 /* IO port 30 */ +#define PORT_31 0x1F00 /* IO port 31 */ +#define PORT_32 0x2000 /* IO port 32 */ +#define PORT_33 0x2100 /* IO port 33 */ +#define PORT_34 0x2200 /* IO port 34 */ +#define PORT_35 0x2300 /* IO port 35 */ +#define PORT_36 0x2400 /* IO port 36 */ +#define PORT_37 0x2500 /* IO port 37 */ +#define PORT_38 0x2600 /* IO port 38 */ +#define PORT_39 0x2700 /* IO port 39 */ +#define PORT_40 0x2800 /* IO port 40 */ +#define PORT_41 0x2900 /* IO port 41 */ +#define PORT_42 0x2A00 /* IO port 42 */ +#define PORT_43 0x2B00 /* IO port 43 */ +#define PORT_44 0x2C00 /* IO port 44 */ +#define PORT_45 0x2D00 /* IO port 45 */ +#define PORT_46 0x2E00 /* IO port 46 */ +#define PORT_47 0x2F00 /* IO port 47 */ +#define PORT_48 0x3000 /* IO port 48 */ + +/* + * Create the value contain port/pin/function information + * + * port: port number BSP_IO_PORT_00..BSP_IO_PORT_48 + * pin: pin number + * func: pin function + */ +#define RZV_PINMUX(port, pin, func) (port | pin | (func << 4)) + +/* Special purpose port */ +#define BSP_IO_NMI 0xFFFF0100 /* NMI */ + +#define BSP_IO_TMS_SWDIO 0xFFFF0200 /* TMS_SWDIO */ + +#define BSP_IO_TDO 0xFFFF0300 /* TDO */ + +#define BSP_IO_AUDIO_CLK1 0xFFFF0400 /* AUDIO_CLK1 */ +#define BSP_IO_AUDIO_CLK2 0xFFFF0401 /* AUDIO_CLK2 */ + +#define BSP_IO_SD0_CLK 0xFFFF0600 /* SD0_CLK */ +#define BSP_IO_SD0_CMD 0xFFFF0601 /* SD0_CMD */ +#define BSP_IO_SD0_RST_N 0xFFFF0602 /* SD0_RST_N */ + +#define BSP_IO_SD0_DATA0 0xFFFF0700 /* SD0_DATA0 */ +#define BSP_IO_SD0_DATA1 0xFFFF0701 /* SD0_DATA1 */ +#define BSP_IO_SD0_DATA2 0xFFFF0702 /* SD0_DATA2 */ +#define BSP_IO_SD0_DATA3 0xFFFF0703 /* SD0_DATA3 */ +#define BSP_IO_SD0_DATA4 0xFFFF0704 /* SD0_DATA4 */ +#define BSP_IO_SD0_DATA5 0xFFFF0705 /* SD0_DATA5 */ +#define BSP_IO_SD0_DATA6 0xFFFF0706 /* SD0_DATA6 */ +#define BSP_IO_SD0_DATA7 0xFFFF0707 /* SD0_DATA7 */ + +#define BSP_IO_SD1_CLK 0xFFFF0800 /* SD1_CLK */ +#define BSP_IO_SD1_CMD 0xFFFF0801 /* SD1_CMD */ + +#define BSP_IO_SD1_DATA0 0xFFFF0900 /* SD1_DATA0 */ +#define BSP_IO_SD1_DATA1 0xFFFF0901 /* SD1_DATA1 */ +#define BSP_IO_SD1_DATA2 0xFFFF0902 /* SD1_DATA2 */ +#define BSP_IO_SD1_DATA3 0xFFFF0903 /* SD1_DATA3 */ + +#define BSP_IO_QSPI0_SPCLK 0xFFFF0A00 /* QSPI0_SPCLK */ +#define BSP_IO_QSPI0_IO0 0xFFFF0A01 /* QSPI0_IO0 */ +#define BSP_IO_QSPI0_IO1 0xFFFF0A02 /* QSPI0_IO1 */ +#define BSP_IO_QSPI0_IO2 0xFFFF0A03 /* QSPI0_IO2 */ +#define BSP_IO_QSPI0_IO3 0xFFFF0A04 /* QSPI0_IO3 */ +#define BSP_IO_QSPI0_SSL 0xFFFF0A05 /* QSPI0_SSL */ + +#define BSP_IO_QSPI1_SPCLK 0xFFFF0B00 /* QSPI1_SPCLK */ +#define BSP_IO_QSPI1_IO0 0xFFFF0B01 /* QSPI1_IO0 */ +#define BSP_IO_QSPI1_IO1 0xFFFF0B02 /* QSPI1_IO1 */ +#define BSP_IO_QSPI1_IO2 0xFFFF0B03 /* QSPI1_IO2 */ +#define BSP_IO_QSPI1_IO3 0xFFFF0B04 /* QSPI1_IO3 */ +#define BSP_IO_QSPI1_SSL 0xFFFF0B05 /* QSPI1_SSL */ + +#define BSP_IO_QSPI_RESET_N 0xFFFF0C00 /* QSPI_RESET_N */ +#define BSP_IO_QSPI_WP_N 0xFFFF0C01 /* QSPI_WP_N */ +#define BSP_IO_QSPI_INT_N 0xFFFF0C02 /* QSPI_INT_N */ + +#define BSP_IO_WDTOVF_PERROUT_N 0xFFFF0D00 /* WDTOVF_PERROUT_N */ + +#define BSP_IO_RIIC0_SDA 0xFFFF0E00 /* RIIC0_SDA */ +#define BSP_IO_RIIC0_SCL 0xFFFF0E01 /* RIIC0_SCL */ +#define BSP_IO_RIIC1_SDA 0xFFFF0E02 /* RIIC1_SDA */ +#define BSP_IO_RIIC1_SCL 0xFFFF0E03 /* RIIC1_SCL */ + +/* FILNUM */ +#define RZV_FILNUM_4_STAGE 0 +#define RZV_FILNUM_8_STAGE 1 +#define RZV_FILNUM_12_STAGE 2 +#define RZV_FILNUM_16_STAGE 3 + +/* FILCLKSEL */ +#define RZV_FILCLKSEL_NOT_DIV 0 +#define RZV_FILCLKSEL_DIV_9000 1 +#define RZV_FILCLKSEL_DIV_18000 2 +#define RZV_FILCLKSEL_DIV_36000 3 + +#define RZV_FILTER_SET(filnum, filclksel) (((filnum) & 0x3) << 0x2) | (filclksel & 0x3) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZV_COMMON_H_ */ diff --git a/soc/renesas/rz/common/pinctrl_rzv.h b/soc/renesas/rz/common/pinctrl_rzv.h new file mode 100644 index 00000000000..a4dd50aef29 --- /dev/null +++ b/soc/renesas/rz/common/pinctrl_rzv.h @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZV_H_ +#define ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZV_H_ + +#include +#include +#include +#include "r_ioport.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Porting */ +typedef struct pinctrl_cfg_data_t { + uint32_t reserved: 4; + uint32_t pupd_reg: 6; + uint32_t iolh_reg: 6; + uint32_t pmc_reg: 1; + uint32_t sr_reg: 1; + uint32_t ien_reg: 1; + uint32_t filonoff_reg: 1; + uint32_t filnum_reg: 2; + uint32_t filclksel_reg: 2; + uint32_t pfc_reg: 3; +} pinctrl_cfg_data_t; + +typedef struct pinctrl_soc_pin_t { + bsp_io_port_pin_t port_pin; + pinctrl_cfg_data_t config; +} pinctrl_soc_pin_t; + +/* Iterate over each pinctrl-n phandle child */ +#define Z_PINCTRL_STATE_PIN_INIT(node_id, state_prop, idx) \ + DT_FOREACH_CHILD(DT_PHANDLE_BY_IDX(node_id, state_prop, idx), \ + Z_PINCTRL_STATE_PIN_CHILD_INIT) + +/* Iterate over each pinctrl-n phandle child */ +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + {DT_FOREACH_PROP_ELEM_SEP(node_id, prop, Z_PINCTRL_STATE_PIN_INIT, ())}; + +#define Z_PINCTRL_STATE_PIN_CHILD_INIT(node_id) \ + COND_CODE_1(DT_NODE_HAS_PROP(node_id, pinmux), \ + (DT_FOREACH_PROP_ELEM(node_id, pinmux, Z_PINCTRL_PINMUX_INIT)), \ + ()) \ + COND_CODE_1(DT_NODE_HAS_PROP(node_id, pins), \ + (DT_FOREACH_PROP_ELEM(node_id, pins, Z_PINCTRL_SPECIAL_PINS_INIT)), \ + ()) + +#define RZV_GET_PORT_PIN(pinmux) (pinmux & ~(0xF << 4)) +#define RZV_GET_FUNC(pinmux) ((pinmux & 0xF0) >> 4) + +#define RZV_GET_PU_PD(node_id) \ + DT_PROP(node_id, bias_pull_up) == 1 ? 1U : (DT_PROP(node_id, bias_pull_down) == 1 ? 2U : 0U) + +#define RZV_GET_FILNUM(node_id) ((DT_PROP(node_id, renesas_filter) >> 2) & 0x3) + +#define RZV_GET_FILCLKSEL(node_id) (DT_PROP(node_id, renesas_filter) & 0x3) + +#define RZV_FILTER_ON_OFF(node_id) COND_CODE_0(DT_PROP(node_id, renesas_filter), (0), (1)) + +/* Process pinmux cfg */ +#define Z_PINCTRL_PINMUX_INIT(node_id, state_prop, idx) \ + { \ + .port_pin = RZV_GET_PORT_PIN(DT_PROP_BY_IDX(node_id, state_prop, idx)), \ + .config = {.reserved = 0, \ + .pupd_reg = RZV_GET_PU_PD(node_id), \ + .iolh_reg = DT_PROP(node_id, drive_strength), \ + .pmc_reg = 1, \ + .sr_reg = DT_ENUM_IDX(node_id, slew_rate), \ + .ien_reg = DT_PROP(node_id, input_enable), \ + .filonoff_reg = RZV_FILTER_ON_OFF(node_id), \ + .filnum_reg = RZV_GET_FILNUM(node_id), \ + .filclksel_reg = RZV_GET_FILCLKSEL(node_id), \ + .pfc_reg = RZV_GET_FUNC(DT_PROP_BY_IDX(node_id, state_prop, idx))}, \ + }, + +#define Z_PINCTRL_SPECIAL_PINS_INIT(node_id, state_prop, idx) \ + { \ + .port_pin = DT_PROP_BY_IDX(node_id, state_prop, idx), \ + .config = \ + { \ + .reserved = 0, \ + .pupd_reg = RZV_GET_PU_PD(node_id), \ + .iolh_reg = DT_PROP(node_id, drive_strength), \ + .pmc_reg = 0, \ + .sr_reg = DT_ENUM_IDX(node_id, slew_rate), \ + .ien_reg = DT_PROP(node_id, input_enable), \ + .filonoff_reg = RZV_FILTER_ON_OFF(node_id), \ + .filnum_reg = RZV_GET_FILNUM(node_id), \ + .filclksel_reg = RZV_GET_FILCLKSEL(node_id), \ + .pfc_reg = 0, \ + }, \ + }, + +#ifdef __cplusplus +} +#endif +#endif /* ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZV_H_ */ diff --git a/soc/renesas/rz/rzv2l/pinctrl_soc.h b/soc/renesas/rz/rzv2l/pinctrl_soc.h new file mode 100644 index 00000000000..e2c055c173d --- /dev/null +++ b/soc/renesas/rz/rzv2l/pinctrl_soc.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_RENESAS_RZ_RZV2L_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RZ_RZV2L_PINCTRL_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RZ_RZV2L_PINCTRL_SOC_H_ */