dts: interrupt_controller: Add dts support for DesignWare controller

Add dts support for multilevel DW interrupt controller

Change-Id: Ia16d6870bd3a46fca933c906aedc6ba78ed5131a
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>

arch/xtensa/soc/intel_s1000/dts.fixup

@@ -8,13 +8,17 @@
 
 #define L2_SRAM_SIZE				CONFIG_SRAM_SIZE_0 * 1024
 
+#define DW_ICTL_BASE_ADDR			SNPS_DESIGNWARE_INTC_81800_BASE_ADDRESS
+
 #define CONFIG_I2C_0_BASE_ADDR			SNPS_DESIGNWARE_I2C_80400_BASE_ADDRESS
 
 #define CONFIG_I2C_0_BITRATE			SNPS_DESIGNWARE_I2C_80400_CLOCK_FREQUENCY
 
 #define CONFIG_I2C_0_NAME			SNPS_DESIGNWARE_I2C_80400_LABEL
 
-#define CONFIG_I2C_0_IRQ			(SNPS_DESIGNWARE_I2C_80400_IRQ_0 << 16) | DW_ICTL_IRQ
+#define CONFIG_I2C_0_IRQ			(SNPS_DESIGNWARE_I2C_80400_IRQ_0 << 16) | \
+						(SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \
+						(INTEL_CAVS_INTC_78800_IRQ_0 << 0)
 
 #define CONFIG_I2C_0_IRQ_FLAGS			SNPS_DESIGNWARE_I2C_80400_IRQ_0_SENSE
 /* End of SoC Level DTS fixup file */

arch/xtensa/soc/intel_s1000/soc.h

@@ -46,7 +46,6 @@
 #define IOAPIC_HIGH				0
 
 /* DW interrupt controller */
-#define DW_ICTL_BASE_ADDR			0x00081800
 #define DW_ICTL_IRQ				0x00000706
 #define DW_ICTL_IRQ_CAVS_OFFSET			CAVS_IRQ_NUMBER(DW_ICTL_IRQ)
 #define DW_ICTL_NUM_IRQS			9

dts/bindings/interrupt-controller/intel,cavs-intc.yaml

@@ -0,0 +1,38 @@
+---
+title: CAVS Interrupt Controller
+version: 0.1
+
+description: >
+    This binding describes CAVS Interrupt controller
+
+properties:
+  compatible:
+      category: required
+      type: string
+      description: compatible strings
+      constraint: "intel,cavs-intc"
+
+  reg:
+      category: required
+      type: int
+      description: mmio register space
+      generation: define
+
+  intel,num-irq-priority-bits:
+      category: required
+      type: int
+      description: number of bits of IRQ priorities
+      generation: define
+
+  interrupts:
+      type: array
+      category: required
+      description: required interrupts
+      generation: define
+
+cell_string: IRQ
+
+"#cells":
+  - irq
+  - sense
+...

dts/bindings/interrupt-controller/snps,designware-intc.yaml

@@ -0,0 +1,38 @@
+---
+title: DesignWare Interrupt Controller
+version: 0.1
+
+description: >
+    This binding describes DesignWare Programmable Interrupt controller
+
+properties:
+  compatible:
+      category: required
+      type: string
+      description: compatible strings
+      constraint: "snps,designware-intc"
+
+  reg:
+      category: required
+      type: int
+      description: mmio register space
+      generation: define
+
+  snps,num-irq-priority-bits:
+      category: required
+      type: int
+      description: number of bits of IRQ priorities
+      generation: define
+
+  interrupts:
+      type: array
+      category: required
+      description: required interrupts
+      generation: define
+
+cell_string: IRQ
+
+"#cells":
+  - irq
+  - sense
+...

dts/bindings/interrupt-controller/xtensa,intc.yaml

@@ -0,0 +1,32 @@
+---
+title: Xtensa Core Interrupt Controller
+version: 0.1
+
+description: >
+    This binding describes Xtensa Core Interrupt controller
+
+properties:
+  compatible:
+      category: required
+      type: string
+      description: compatible strings
+      constraint: "xtensa,core-intc"
+
+  reg:
+      category: required
+      type: int
+      description: mmio register space
+      generation: define
+
+  snps,num-irq-priority-bits:
+      category: required
+      type: int
+      description: number of bits of IRQ priorities
+      generation: define
+
+cell_string: IRQ
+
+"#cells":
+  - irq
+  - sense
+...

dts/xtensa/intel_s1000.dtsi

@@ -20,6 +20,13 @@
 			reg = <1>;
 		};
 
+		core_intc: core_intc@0 {
+			compatible = "xtensa,core-intc";
+			reg = <0x00 0x400>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
 	};
 
 	sram0: memory@0xbe000000 {
@@ -34,6 +41,46 @@
 		compatible = "simple-bus";
 		ranges;
 
+		cavs0: cavs@78800  {
+			compatible = "intel,cavs-intc";
+			reg = <0x78800 0x10>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupts = <6 0>;
+			interrupt-parent = <&core_intc>;
+		};
+
+		cavs1: cavs@78810  {
+			compatible = "intel,cavs-intc";
+			reg = <0x78810 0x10>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		cavs2: cavs@78820  {
+			compatible = "intel,cavs-intc";
+			reg = <0x78820 0x10>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		cavs3: cavs@78830  {
+			compatible = "intel,cavs-intc";
+			reg = <0x78830 0x10>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		dw_intc: intc@81800  {
+			compatible = "snps,designware-intc";
+			reg = <0x00081800 0x400>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupts = <7 0>;
+			interrupt-parent = <&cavs0>;
+		};
+
+
 		uart0: uart@80800 {
 			compatible = "ns16550";
 			reg = <0x80800 0x400>;
@@ -49,7 +96,7 @@
 			#size-cells = <0>;
 			reg = <0x80400 0x400>;
 			interrupts = <2 0>;
-			interrupt-parent = <&intc>;
+			interrupt-parent = <&dw_intc>;
 			label = "I2C_0";
 
 			status = "disabled";