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board: arc: hsdk: Initialize core0 in the end

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The last core which gets initilaized is used by default by OpenOCD.
Thus if we leave configuration as it was we'll get single-core
binaries executed by core3 while we expect core0 to be used.

We didn't see that problem reviously because we used to use
GDB for binary (actually Elf) loading and execution and there in GDB
we explicitly connected to the OpenOCD port wired to core 0.

Now with "west flash" we use OpenOCD for loading anr running and
we need everything setup correctly from the beginning.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This commit is contained in:
Alexey Brodkin 2020-02-12 11:59:14 +03:00 • committed by Johan Hedberg
commit 7a8c624f53
1 changed files with 13 additions and 16 deletions
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29
boards/arc/hsdk/support/openocd.cfg
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@ -50,22 +50,6 @@ jtag newtap $_CHIPNAME cpu2 -irlen 4 -ircapture 0x1 -expected-id 0x200424b1
set _TARGETNAME1 $_CHIPNAME.cpu1
jtag newtap $_CHIPNAME cpu1 -irlen 4 -ircapture 0x1 -expected-id 0x200024b1
################################
# ARC HS38 core 1
################################
target create $_TARGETNAME1 arcv2 -chain-position $_TARGETNAME1
$_TARGETNAME1 configure -coreid $_coreid
$_TARGETNAME1 configure -dbgbase $_dbgbase
$_TARGETNAME1 configure -event reset-assert "arc_common_reset $_TARGETNAME1"
set _coreid [expr $_coreid + 1]
set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
arc_hs_init_regs
# Enable L2 cache support for core 1.
$_TARGETNAME1 arc has-l2cache true
################################
# ARC HS38 core 2
################################
@ -113,6 +97,19 @@ arc_hs_init_regs
# Enable L2 cache support for core 4.
$_TARGETNAME4 arc has-l2cache true
################################
# ARC HS38 core 1
################################
target create $_TARGETNAME1 arcv2 -chain-position $_TARGETNAME1
$_TARGETNAME1 configure -coreid $_coreid
$_TARGETNAME1 configure -dbgbase $_dbgbase
$_TARGETNAME1 configure -event reset-assert "arc_common_reset $_TARGETNAME1"
set _coreid [expr $_coreid + 1]
set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
arc_hs_init_regs
# Enable L2 cache support for core 1.
$_TARGETNAME1 arc has-l2cache true
# vi:ft=tcl