diff --git a/boards/arc/hsdk/support/openocd.cfg b/boards/arc/hsdk/support/openocd.cfg
index 957d60a40d8..28a59e953c6 100644
--- a/boards/arc/hsdk/support/openocd.cfg
+++ b/boards/arc/hsdk/support/openocd.cfg
@@ -50,22 +50,6 @@ jtag newtap $_CHIPNAME cpu2 -irlen 4 -ircapture 0x1 -expected-id 0x200424b1
 set _TARGETNAME1 $_CHIPNAME.cpu1
 jtag newtap $_CHIPNAME cpu1 -irlen 4 -ircapture 0x1 -expected-id 0x200024b1
 
-################################
-# ARC HS38 core 1
-################################
-
-target create $_TARGETNAME1 arcv2 -chain-position $_TARGETNAME1
-$_TARGETNAME1 configure -coreid $_coreid
-$_TARGETNAME1 configure -dbgbase $_dbgbase
-$_TARGETNAME1 configure -event reset-assert "arc_common_reset $_TARGETNAME1"
-set _coreid [expr $_coreid + 1]
-set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
-arc_hs_init_regs
-
-# Enable L2 cache support for core 1.
-$_TARGETNAME1 arc has-l2cache true
-
-
 ################################
 # ARC HS38 core 2
 ################################
@@ -113,6 +97,19 @@ arc_hs_init_regs
 # Enable L2 cache support for core 4.
 $_TARGETNAME4 arc has-l2cache true
 
+################################
+# ARC HS38 core 1
+################################
 
+target create $_TARGETNAME1 arcv2 -chain-position $_TARGETNAME1
+$_TARGETNAME1 configure -coreid $_coreid
+$_TARGETNAME1 configure -dbgbase $_dbgbase
+$_TARGETNAME1 configure -event reset-assert "arc_common_reset $_TARGETNAME1"
+set _coreid [expr $_coreid + 1]
+set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
+arc_hs_init_regs
+
+# Enable L2 cache support for core 1.
+$_TARGETNAME1 arc has-l2cache true
 
 # vi:ft=tcl