arch: arm: cortex_m: Revert "enable armv8m.baseline to use BASEPRI"
This reverts commit 0781a86862
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BASEPRI is only functionnal if mainline extension is present.
If not, it is "RES0". See: Arm®v8-M Architecture Reference Manual D1.2.5.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
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3de98643ed
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7a216d2a69
1 changed files with 6 additions and 14 deletions
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@ -43,8 +43,8 @@ static ALWAYS_INLINE unsigned int arch_irq_lock(void)
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{
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unsigned int key;
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) && !defined(CONFIG_ARMV8_M_BASELINE)
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#if CONFIG_MP_MAX_NUM_CPUS == 1
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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#if CONFIG_MP_MAX_NUM_CPUS == 1 || defined(CONFIG_ARMV8_M_BASELINE)
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__asm__ volatile("mrs %0, PRIMASK;"
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"cpsid i"
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: "=r" (key)
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@ -53,7 +53,7 @@ static ALWAYS_INLINE unsigned int arch_irq_lock(void)
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#else
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#error "Cortex-M0 and Cortex-M0+ require SoC specific support for cross core synchronisation."
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#endif
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) || defined(CONFIG_ARMV8_M_BASELINE)
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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unsigned int tmp;
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__asm__ volatile(
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@ -61,15 +61,7 @@ static ALWAYS_INLINE unsigned int arch_irq_lock(void)
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"mrs %0, BASEPRI;"
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"msr BASEPRI_MAX, %1;"
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"isb;"
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: "=r"(key),
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#if defined(CONFIG_ARMV8_M_BASELINE)
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/* armv8-m.baseline's mov is limited to registers r0-r7.
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* Let the compiler know we have this constraint on tmp.
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*/
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"=l"(tmp)
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#else
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"=r"(tmp)
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#endif
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: "=r"(key), "=r"(tmp)
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: "i"(_EXC_IRQ_DEFAULT_PRIO)
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: "memory");
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#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \
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@ -95,7 +87,7 @@ static ALWAYS_INLINE unsigned int arch_irq_lock(void)
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static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
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{
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) && !defined(CONFIG_ARMV8_M_BASELINE)
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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if (key != 0U) {
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return;
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}
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@ -103,7 +95,7 @@ static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
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"cpsie i;"
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"isb"
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: : : "memory");
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) || defined(CONFIG_ARMV8_M_BASELINE)
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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__asm__ volatile(
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"msr BASEPRI, %0;"
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"isb;"
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