arch: arm: cortex_m: enable armv8m.baseline to use BASEPRI based irq lock
This allows for armv8m.baseline cores to rely on BASEPRI based interrupt masking and share the same code as v7m and v8m.mainline. Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
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0781a86862
1 changed files with 8 additions and 4 deletions
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@ -43,13 +43,17 @@ static ALWAYS_INLINE unsigned int arch_irq_lock(void)
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{
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unsigned int key;
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) && !defined(CONFIG_ARMV8_M_BASELINE)
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#if CONFIG_MP_MAX_NUM_CPUS == 1
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__asm__ volatile("mrs %0, PRIMASK;"
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"cpsid i"
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: "=r" (key)
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:
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: "memory");
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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#else
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#error "Cortex-M0 and Cortex-M0+ require SoC specific support for cross core synchronisation."
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#endif
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) || defined(CONFIG_ARMV8_M_BASELINE)
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unsigned int tmp;
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__asm__ volatile(
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@ -83,7 +87,7 @@ static ALWAYS_INLINE unsigned int arch_irq_lock(void)
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static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
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{
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) && !defined(CONFIG_ARMV8_M_BASELINE)
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if (key != 0U) {
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return;
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}
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@ -91,7 +95,7 @@ static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
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"cpsie i;"
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"isb"
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: : : "memory");
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) || defined(CONFIG_ARMV8_M_BASELINE)
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__asm__ volatile(
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"msr BASEPRI, %0;"
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"isb;"
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