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drivers: spi: Add STM32G4X SPI support

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Add SPI driver support for STM32G4X SoC series.

Signed-off-by: Richard Osterloh <richard.osterloh@gmail.com>
This commit is contained in:
Richard Osterloh 2019-09-04 09:45:03 +01:00 • committed by Andrew Boie
commit 794606f866
4 changed files with 59 additions and 1 deletions
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2
drivers/spi/Kconfig.stm32
View file

@ -19,7 +19,7 @@ config SPI_STM32_HAS_FIFO
bool bool
depends on (SOC_SERIES_STM32L4X || SOC_SERIES_STM32F0X || \ depends on (SOC_SERIES_STM32L4X || SOC_SERIES_STM32F0X || \
SOC_SERIES_STM32F3X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32MP1X || \ SOC_SERIES_STM32F3X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32MP1X || \
SOC_SERIES_STM32WBX) SOC_SERIES_STM32WBX || SOC_SERIES_STM32G4X)
default y default y
config SPI_STM32_INTERRUPT config SPI_STM32_INTERRUPT

33
dts/arm/st/g4/stm32g4.dtsi
View file

@ -206,6 +206,39 @@
label= "I2C_3"; label= "I2C_3";
}; };
spi1: spi@40013000 {
compatible = "st,stm32-spi-fifo";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40013000 0x400>;
interrupts = <35 5>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
status = "disabled";
label = "SPI_1";
};
spi2: spi@40003800 {
compatible = "st,stm32-spi-fifo";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
interrupts = <36 5>;
status = "disabled";
label = "SPI_2";
};
spi3: spi@40003c00 {
compatible = "st,stm32-spi-fifo";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
interrupts = <51 5>;
status = "disabled";
label = "SPI_3";
};
}; };
}; };

21
soc/arm/st_stm32/stm32g4/dts_fixup.h
View file

@ -149,4 +149,25 @@
#define DT_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V2_40007800_CLOCK_BITS #define DT_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V2_40007800_CLOCK_BITS
#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40007800_CLOCK_BUS #define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40007800_CLOCK_BUS
#define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS
#define DT_SPI_1_IRQ_PRI DT_ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY
#define DT_SPI_1_NAME DT_ST_STM32_SPI_FIFO_40013000_LABEL
#define DT_SPI_1_IRQ DT_ST_STM32_SPI_FIFO_40013000_IRQ_0
#define DT_SPI_1_CLOCK_BITS DT_ST_STM32_SPI_FIFO_40013000_CLOCK_BITS
#define DT_SPI_1_CLOCK_BUS DT_ST_STM32_SPI_FIFO_40013000_CLOCK_BUS
#define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS
#define DT_SPI_2_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY
#define DT_SPI_2_NAME DT_ST_STM32_SPI_FIFO_40003800_LABEL
#define DT_SPI_2_IRQ DT_ST_STM32_SPI_FIFO_40003800_IRQ_0
#define DT_SPI_2_CLOCK_BITS DT_ST_STM32_SPI_FIFO_40003800_CLOCK_BITS
#define DT_SPI_2_CLOCK_BUS DT_ST_STM32_SPI_FIFO_40003800_CLOCK_BUS
#define DT_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003C00_BASE_ADDRESS
#define DT_SPI_3_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003C00_IRQ_0_PRIORITY
#define DT_SPI_3_NAME DT_ST_STM32_SPI_FIFO_40003C00_LABEL
#define DT_SPI_3_IRQ DT_ST_STM32_SPI_FIFO_40003C00_IRQ_0
#define DT_SPI_3_CLOCK_BITS DT_ST_STM32_SPI_FIFO_40003C00_CLOCK_BITS
#define DT_SPI_3_CLOCK_BUS DT_ST_STM32_SPI_FIFO_40003C00_CLOCK_BUS
/* End of SoC Level DTS fixup file */ /* End of SoC Level DTS fixup file */

4
soc/arm/st_stm32/stm32g4/soc.h
View file

@ -48,6 +48,10 @@
#include <stm32g4xx_ll_lpuart.h> #include <stm32g4xx_ll_lpuart.h>
#endif /* CONFIG_SERIAL_HAS_DRIVER */ #endif /* CONFIG_SERIAL_HAS_DRIVER */
#ifdef CONFIG_SPI_STM32
#include <stm32g4xx_ll_spi.h>
#endif
#ifdef CONFIG_I2C #ifdef CONFIG_I2C
#include <stm32g4xx_ll_i2c.h> #include <stm32g4xx_ll_i2c.h>
#endif /* CONFIG_I2C */ #endif /* CONFIG_I2C */