diff --git a/drivers/spi/Kconfig.stm32 b/drivers/spi/Kconfig.stm32
index 1147d8b46e2..f1bfccaba96 100644
--- a/drivers/spi/Kconfig.stm32
+++ b/drivers/spi/Kconfig.stm32
@@ -19,7 +19,7 @@ config SPI_STM32_HAS_FIFO
 	bool
 	depends on (SOC_SERIES_STM32L4X || SOC_SERIES_STM32F0X || \
 	SOC_SERIES_STM32F3X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32MP1X || \
-	SOC_SERIES_STM32WBX)
+	SOC_SERIES_STM32WBX || SOC_SERIES_STM32G4X)
 	default y
 
 config SPI_STM32_INTERRUPT
diff --git a/dts/arm/st/g4/stm32g4.dtsi b/dts/arm/st/g4/stm32g4.dtsi
index b2616fa87c6..81033bc9d70 100644
--- a/dts/arm/st/g4/stm32g4.dtsi
+++ b/dts/arm/st/g4/stm32g4.dtsi
@@ -206,6 +206,39 @@
 			label= "I2C_3";
 		};
 
+		spi1: spi@40013000 {
+			compatible = "st,stm32-spi-fifo";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40013000 0x400>;
+			interrupts = <35 5>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			status = "disabled";
+			label = "SPI_1";
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32-spi-fifo";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			interrupts = <36 5>;
+			status = "disabled";
+			label = "SPI_2";
+		};
+
+		spi3: spi@40003c00 {
+			compatible = "st,stm32-spi-fifo";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003c00 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			interrupts = <51 5>;
+			status = "disabled";
+			label = "SPI_3";
+		};
+
 	};
 
 };
diff --git a/soc/arm/st_stm32/stm32g4/dts_fixup.h b/soc/arm/st_stm32/stm32g4/dts_fixup.h
index a5db1a1c85f..60326acfc51 100644
--- a/soc/arm/st_stm32/stm32g4/dts_fixup.h
+++ b/soc/arm/st_stm32/stm32g4/dts_fixup.h
@@ -149,4 +149,25 @@
 #define DT_I2C_3_CLOCK_BITS			DT_ST_STM32_I2C_V2_40007800_CLOCK_BITS
 #define DT_I2C_3_CLOCK_BUS			DT_ST_STM32_I2C_V2_40007800_CLOCK_BUS
 
+#define DT_SPI_1_BASE_ADDRESS			DT_ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS
+#define DT_SPI_1_IRQ_PRI			DT_ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY
+#define DT_SPI_1_NAME				DT_ST_STM32_SPI_FIFO_40013000_LABEL
+#define DT_SPI_1_IRQ				DT_ST_STM32_SPI_FIFO_40013000_IRQ_0
+#define DT_SPI_1_CLOCK_BITS			DT_ST_STM32_SPI_FIFO_40013000_CLOCK_BITS
+#define DT_SPI_1_CLOCK_BUS			DT_ST_STM32_SPI_FIFO_40013000_CLOCK_BUS
+
+#define DT_SPI_2_BASE_ADDRESS			DT_ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS
+#define DT_SPI_2_IRQ_PRI			DT_ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY
+#define DT_SPI_2_NAME				DT_ST_STM32_SPI_FIFO_40003800_LABEL
+#define DT_SPI_2_IRQ				DT_ST_STM32_SPI_FIFO_40003800_IRQ_0
+#define DT_SPI_2_CLOCK_BITS			DT_ST_STM32_SPI_FIFO_40003800_CLOCK_BITS
+#define DT_SPI_2_CLOCK_BUS			DT_ST_STM32_SPI_FIFO_40003800_CLOCK_BUS
+
+#define DT_SPI_3_BASE_ADDRESS			DT_ST_STM32_SPI_FIFO_40003C00_BASE_ADDRESS
+#define DT_SPI_3_IRQ_PRI			DT_ST_STM32_SPI_FIFO_40003C00_IRQ_0_PRIORITY
+#define DT_SPI_3_NAME				DT_ST_STM32_SPI_FIFO_40003C00_LABEL
+#define DT_SPI_3_IRQ				DT_ST_STM32_SPI_FIFO_40003C00_IRQ_0
+#define DT_SPI_3_CLOCK_BITS			DT_ST_STM32_SPI_FIFO_40003C00_CLOCK_BITS
+#define DT_SPI_3_CLOCK_BUS			DT_ST_STM32_SPI_FIFO_40003C00_CLOCK_BUS
+
 /* End of SoC Level DTS fixup file */
diff --git a/soc/arm/st_stm32/stm32g4/soc.h b/soc/arm/st_stm32/stm32g4/soc.h
index f7cbf7ea9aa..f5b3e19e244 100644
--- a/soc/arm/st_stm32/stm32g4/soc.h
+++ b/soc/arm/st_stm32/stm32g4/soc.h
@@ -48,6 +48,10 @@
 #include <stm32g4xx_ll_lpuart.h>
 #endif /* CONFIG_SERIAL_HAS_DRIVER */
 
+#ifdef CONFIG_SPI_STM32
+#include <stm32g4xx_ll_spi.h>
+#endif
+
 #ifdef CONFIG_I2C
 #include <stm32g4xx_ll_i2c.h>
 #endif /* CONFIG_I2C */