boards: s32z2xxdc2: add support for adc

Add devicetree of adc instances for s32z270.

Signed-off-by: Ha Duong Quang <ha.duongquang@nxp.com>

boards/nxp/s32z2xxdc2/doc/index.rst

@@ -55,6 +55,8 @@ The boards support the following hardware features:
 +-----------+------------+-------------------------------------+
 | FLEXCAN   | on-chip    | can                                 |
 +-----------+------------+-------------------------------------+
+| SAR_ADC   | on-chip    | adc                                 |
++-----------+------------+-------------------------------------+
 
 Other hardware features are not currently supported by the port.
 
@@ -150,6 +152,15 @@ FlexCAN
 
 FlexCAN supports CAN Classic (CAN 2.0) and CAN FD modes.
 
+ADC
+===
+
+ADC is provided through ADC SAR controller with 2 instances. Each ADC SAR instance has
+12-bit resolution. ADC channels are divided into 2 groups (precision and internal/standard).
+
+.. note::
+   All channels of an instance only run on 1 group channel at the same time.
+
 Programming and Debugging
 *************************
 

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi

@@ -50,3 +50,11 @@
 	pinctrl-0 = <&flexcan1_default>;
 	pinctrl-names = "default";
 };
+
+&sar_adc0 {
+	vref-mv = <1800>;
+};
+
+&sar_adc1 {
+	vref-mv = <1800>;
+};

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml

@@ -16,4 +16,5 @@ supported:
   - can
   - spi
   - counter
+  - adc
 vendor: nxp

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml

@@ -16,4 +16,5 @@ supported:
   - can
   - spi
   - counter
+  - adc
 vendor: nxp

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml

@@ -16,4 +16,5 @@ supported:
   - can
   - spi
   - counter
+  - adc
 vendor: nxp

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml

@@ -16,4 +16,5 @@ supported:
   - can
   - spi
   - counter
+  - adc
 vendor: nxp

drivers/adc/adc_nxp_s32_adc_sar.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2023 NXP
+ * Copyright 2023-2024 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -403,6 +403,18 @@ static void adc_nxp_s32_isr(const struct device *dev)
 #define ADC_NXP_S32_GET_INSTANCE(n)		\
 	LISTIFY(__DEBRACKET ADC_INSTANCE_COUNT, ADC_NXP_S32_INSTANCE_CHECK, (|), n)
 
+#if (FEATURE_ADC_HAS_HIGH_SPEED_ENABLE == 1U)
+#define ADC_NXP_S32_HIGH_SPEED_CFG(n) .HighSpeedConvEn = DT_INST_PROP(n, high_speed),
+#else
+#define ADC_NXP_S32_HIGH_SPEED_CFG(n)
+#endif
+
+#if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
+#define ADC_NXP_S32_RESOLUTION_CFG(n) .AdcResolution = ADC_SAR_IP_RESOLUTION_14,
+#else
+#define ADC_NXP_S32_RESOLUTION_CFG(n)
+#endif
+
 #define ADC_NXP_S32_INIT_DEVICE(n)						\
 	ADC_NXP_S32_DRIVER_API(n)						\
 	ADC_NXP_S32_CALLBACK_DEFINE(n)						\
@@ -412,8 +424,8 @@ static void adc_nxp_s32_isr(const struct device *dev)
 	static const Adc_Sar_Ip_ConfigType adc_nxp_s32_default_config##n =	\
 	{									\
 		.ConvMode = ADC_SAR_IP_CONV_MODE_ONESHOT,			\
-		.AdcResolution = ADC_SAR_IP_RESOLUTION_14,			\
+		ADC_NXP_S32_RESOLUTION_CFG(n)					\
-		.HighSpeedConvEn = DT_INST_PROP(n, high_speed),			\
+		ADC_NXP_S32_HIGH_SPEED_CFG(n)					\
 		.EndOfNormalChainNotification =					\
 				adc_nxp_s32_normal_endchain_callback##n,	\
 		.EndOfConvNotification =					\

dts/arm/nxp/nxp_s32z27x_r52.dtsi

@@ -1074,5 +1074,25 @@
 			status = "disabled";
 		};
 
+		sar_adc0: adc@402c0000 {
+			compatible = "nxp,s32-adc-sar";
+			reg = <0x402C0000 0x1000>;
+			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 169 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 170 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			#io-channel-cells = <1>;
+			status = "disabled";
+		};
+
+		sar_adc1: adc@402e0000 {
+			compatible = "nxp,s32-adc-sar";
+			reg = <0x402e0000 0x1000>;
+			interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 202 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 203 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			#io-channel-cells = <1>;
+			status = "disabled";
+		};
+
 	};
 };

west.yml

@@ -198,7 +198,7 @@ manifest:
       groups:
         - hal
     - name: hal_nxp
-      revision: e400b5dba27d9abe1403fc799d48b58fa1b1daee
+      revision: 00fd3f5a3b1b7fc3a715b1e96cb2d5036b5cc27e
       path: modules/hal/nxp
       groups:
         - hal