From 77968d4dd884850b72994b405b7111811e6d20ab Mon Sep 17 00:00:00 2001 From: Ha Duong Quang Date: Wed, 21 Aug 2024 17:19:59 +0700 Subject: [PATCH] boards: s32z2xxdc2: add support for adc Add devicetree of adc instances for s32z270. Signed-off-by: Ha Duong Quang --- boards/nxp/s32z2xxdc2/doc/index.rst | 11 ++++++++++ boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi | 8 ++++++++ .../s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml | 1 + .../s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml | 1 + .../s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml | 1 + .../s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml | 1 + drivers/adc/adc_nxp_s32_adc_sar.c | 18 ++++++++++++++--- dts/arm/nxp/nxp_s32z27x_r52.dtsi | 20 +++++++++++++++++++ west.yml | 2 +- 9 files changed, 59 insertions(+), 4 deletions(-) diff --git a/boards/nxp/s32z2xxdc2/doc/index.rst b/boards/nxp/s32z2xxdc2/doc/index.rst index 4efafdf0ffd..07176338995 100644 --- a/boards/nxp/s32z2xxdc2/doc/index.rst +++ b/boards/nxp/s32z2xxdc2/doc/index.rst @@ -55,6 +55,8 @@ The boards support the following hardware features: +-----------+------------+-------------------------------------+ | FLEXCAN | on-chip | can | +-----------+------------+-------------------------------------+ +| SAR_ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ Other hardware features are not currently supported by the port. @@ -150,6 +152,15 @@ FlexCAN FlexCAN supports CAN Classic (CAN 2.0) and CAN FD modes. +ADC +=== + +ADC is provided through ADC SAR controller with 2 instances. Each ADC SAR instance has +12-bit resolution. ADC channels are divided into 2 groups (precision and internal/standard). + +.. note:: + All channels of an instance only run on 1 group channel at the same time. + Programming and Debugging ************************* diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi index 6cd0c45a8bd..65f04794ce3 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi @@ -50,3 +50,11 @@ pinctrl-0 = <&flexcan1_default>; pinctrl-names = "default"; }; + +&sar_adc0 { + vref-mv = <1800>; +}; + +&sar_adc1 { + vref-mv = <1800>; +}; diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml index 9bbb05c6414..0c7edbc17aa 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml @@ -16,4 +16,5 @@ supported: - can - spi - counter + - adc vendor: nxp diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml index 75d0455ee59..ef69cef76b2 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml @@ -16,4 +16,5 @@ supported: - can - spi - counter + - adc vendor: nxp diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml index 77a57961550..6efb13dd793 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml @@ -16,4 +16,5 @@ supported: - can - spi - counter + - adc vendor: nxp diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml index 1d99009466c..9b3c20aeae8 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml @@ -16,4 +16,5 @@ supported: - can - spi - counter + - adc vendor: nxp diff --git a/drivers/adc/adc_nxp_s32_adc_sar.c b/drivers/adc/adc_nxp_s32_adc_sar.c index 7cb5baf5b5c..e4c9f269b72 100644 --- a/drivers/adc/adc_nxp_s32_adc_sar.c +++ b/drivers/adc/adc_nxp_s32_adc_sar.c @@ -1,5 +1,5 @@ /* - * Copyright 2023 NXP + * Copyright 2023-2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -403,6 +403,18 @@ static void adc_nxp_s32_isr(const struct device *dev) #define ADC_NXP_S32_GET_INSTANCE(n) \ LISTIFY(__DEBRACKET ADC_INSTANCE_COUNT, ADC_NXP_S32_INSTANCE_CHECK, (|), n) +#if (FEATURE_ADC_HAS_HIGH_SPEED_ENABLE == 1U) +#define ADC_NXP_S32_HIGH_SPEED_CFG(n) .HighSpeedConvEn = DT_INST_PROP(n, high_speed), +#else +#define ADC_NXP_S32_HIGH_SPEED_CFG(n) +#endif + +#if (ADC_SAR_IP_SET_RESOLUTION == STD_ON) +#define ADC_NXP_S32_RESOLUTION_CFG(n) .AdcResolution = ADC_SAR_IP_RESOLUTION_14, +#else +#define ADC_NXP_S32_RESOLUTION_CFG(n) +#endif + #define ADC_NXP_S32_INIT_DEVICE(n) \ ADC_NXP_S32_DRIVER_API(n) \ ADC_NXP_S32_CALLBACK_DEFINE(n) \ @@ -412,8 +424,8 @@ static void adc_nxp_s32_isr(const struct device *dev) static const Adc_Sar_Ip_ConfigType adc_nxp_s32_default_config##n = \ { \ .ConvMode = ADC_SAR_IP_CONV_MODE_ONESHOT, \ - .AdcResolution = ADC_SAR_IP_RESOLUTION_14, \ - .HighSpeedConvEn = DT_INST_PROP(n, high_speed), \ + ADC_NXP_S32_RESOLUTION_CFG(n) \ + ADC_NXP_S32_HIGH_SPEED_CFG(n) \ .EndOfNormalChainNotification = \ adc_nxp_s32_normal_endchain_callback##n, \ .EndOfConvNotification = \ diff --git a/dts/arm/nxp/nxp_s32z27x_r52.dtsi b/dts/arm/nxp/nxp_s32z27x_r52.dtsi index bd410844e4e..bd3affdaad3 100644 --- a/dts/arm/nxp/nxp_s32z27x_r52.dtsi +++ b/dts/arm/nxp/nxp_s32z27x_r52.dtsi @@ -1074,5 +1074,25 @@ status = "disabled"; }; + sar_adc0: adc@402c0000 { + compatible = "nxp,s32-adc-sar"; + reg = <0x402C0000 0x1000>; + interrupts = , + , + ; + #io-channel-cells = <1>; + status = "disabled"; + }; + + sar_adc1: adc@402e0000 { + compatible = "nxp,s32-adc-sar"; + reg = <0x402e0000 0x1000>; + interrupts = , + , + ; + #io-channel-cells = <1>; + status = "disabled"; + }; + }; }; diff --git a/west.yml b/west.yml index 73c5bd1c424..0f5298cad19 100644 --- a/west.yml +++ b/west.yml @@ -198,7 +198,7 @@ manifest: groups: - hal - name: hal_nxp - revision: e400b5dba27d9abe1403fc799d48b58fa1b1daee + revision: 00fd3f5a3b1b7fc3a715b1e96cb2d5036b5cc27e path: modules/hal/nxp groups: - hal