arm: cortex_r: add support for thread local storage

Adds the necessary bits to initialize TLS in the stack
area and sets up CPU registers during context switch.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung 2020-09-29 12:03:14 -07:00 committed by Andrew Boie
commit 778c996831
4 changed files with 18 additions and 1 deletions

View file

@ -32,7 +32,7 @@ config ARM
# FIXME: current state of the code for all ARM requires this, but
# is really only necessary for Cortex-M with ARM MPU!
select GEN_PRIV_STACKS
select ARCH_HAS_THREAD_LOCAL_STORAGE if ARM64
select ARCH_HAS_THREAD_LOCAL_STORAGE if ARM64 || CPU_CORTEX_R
help
ARM architecture

View file

@ -23,6 +23,7 @@ zephyr_library_sources_ifdef(CONFIG_GEN_SW_ISR_TABLE isr_wrapper.S)
zephyr_library_sources_ifdef(CONFIG_CPLUSPLUS __aeabi_atexit.c)
zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
zephyr_library_sources_ifdef(CONFIG_SW_VECTOR_RELAY irq_relay.S)
zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE ../common/tls.c)
zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S)
add_subdirectory_ifdef(CONFIG_CPU_CORTEX_M cortex_m)

View file

@ -167,6 +167,21 @@ out_fp_endif:
str v3, [v4, #0]
#endif
#if defined(CONFIG_THREAD_LOCAL_STORAGE)
/* Grab the TLS pointer */
ldr r4, =_thread_offset_to_tls
adds r4, r2, r4
ldr r0, [r4]
#if defined(CONFIG_CPU_CORTEX_R)
/* Store TLS pointer in the "Process ID" register.
* This register is used as a base pointer to all
* thread variables with offsets added by toolchain.
*/
mcr 15, 0, r0, cr13, cr0, 3
#endif
#endif
/* Restore previous interrupt disable state (irq_lock key)
* (We clear the arch.basepri field after restoring state)
*/

View file

@ -174,6 +174,7 @@ SECTIONS
_image_rodata_start = .;
#include <linker/common-rom.ld>
#include <linker/thread-local-storage.ld>
SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
{