arm: cortex_r: add support for thread local storage
Adds the necessary bits to initialize TLS in the stack area and sets up CPU registers during context switch. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
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4 changed files with 18 additions and 1 deletions
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@ -32,7 +32,7 @@ config ARM
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# FIXME: current state of the code for all ARM requires this, but
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# is really only necessary for Cortex-M with ARM MPU!
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select GEN_PRIV_STACKS
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select ARCH_HAS_THREAD_LOCAL_STORAGE if ARM64
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select ARCH_HAS_THREAD_LOCAL_STORAGE if ARM64 || CPU_CORTEX_R
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help
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ARM architecture
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@ -23,6 +23,7 @@ zephyr_library_sources_ifdef(CONFIG_GEN_SW_ISR_TABLE isr_wrapper.S)
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zephyr_library_sources_ifdef(CONFIG_CPLUSPLUS __aeabi_atexit.c)
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zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
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zephyr_library_sources_ifdef(CONFIG_SW_VECTOR_RELAY irq_relay.S)
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zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE ../common/tls.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S)
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add_subdirectory_ifdef(CONFIG_CPU_CORTEX_M cortex_m)
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@ -167,6 +167,21 @@ out_fp_endif:
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str v3, [v4, #0]
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#endif
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#if defined(CONFIG_THREAD_LOCAL_STORAGE)
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/* Grab the TLS pointer */
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ldr r4, =_thread_offset_to_tls
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adds r4, r2, r4
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ldr r0, [r4]
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#if defined(CONFIG_CPU_CORTEX_R)
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/* Store TLS pointer in the "Process ID" register.
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* This register is used as a base pointer to all
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* thread variables with offsets added by toolchain.
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*/
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mcr 15, 0, r0, cr13, cr0, 3
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#endif
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#endif
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/* Restore previous interrupt disable state (irq_lock key)
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* (We clear the arch.basepri field after restoring state)
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*/
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@ -174,6 +174,7 @@ SECTIONS
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_image_rodata_start = .;
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#include <linker/common-rom.ld>
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#include <linker/thread-local-storage.ld>
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SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
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{
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