From 778c996831e7f7a0063f115853986d8810ed9aed Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Tue, 29 Sep 2020 12:03:14 -0700 Subject: [PATCH] arm: cortex_r: add support for thread local storage Adds the necessary bits to initialize TLS in the stack area and sets up CPU registers during context switch. Signed-off-by: Daniel Leung --- arch/Kconfig | 2 +- arch/arm/core/aarch32/CMakeLists.txt | 1 + arch/arm/core/aarch32/swap_helper.S | 15 +++++++++++++++ .../arch/arm/aarch32/cortex_a_r/scripts/linker.ld | 1 + 4 files changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/Kconfig b/arch/Kconfig index 1d973fc4063..c4c31a59232 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -32,7 +32,7 @@ config ARM # FIXME: current state of the code for all ARM requires this, but # is really only necessary for Cortex-M with ARM MPU! select GEN_PRIV_STACKS - select ARCH_HAS_THREAD_LOCAL_STORAGE if ARM64 + select ARCH_HAS_THREAD_LOCAL_STORAGE if ARM64 || CPU_CORTEX_R help ARM architecture diff --git a/arch/arm/core/aarch32/CMakeLists.txt b/arch/arm/core/aarch32/CMakeLists.txt index 4d2898970ef..121969faf20 100644 --- a/arch/arm/core/aarch32/CMakeLists.txt +++ b/arch/arm/core/aarch32/CMakeLists.txt @@ -23,6 +23,7 @@ zephyr_library_sources_ifdef(CONFIG_GEN_SW_ISR_TABLE isr_wrapper.S) zephyr_library_sources_ifdef(CONFIG_CPLUSPLUS __aeabi_atexit.c) zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c) zephyr_library_sources_ifdef(CONFIG_SW_VECTOR_RELAY irq_relay.S) +zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE ../common/tls.c) zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S) add_subdirectory_ifdef(CONFIG_CPU_CORTEX_M cortex_m) diff --git a/arch/arm/core/aarch32/swap_helper.S b/arch/arm/core/aarch32/swap_helper.S index 05a5967e754..d9bd3fdf606 100644 --- a/arch/arm/core/aarch32/swap_helper.S +++ b/arch/arm/core/aarch32/swap_helper.S @@ -167,6 +167,21 @@ out_fp_endif: str v3, [v4, #0] #endif +#if defined(CONFIG_THREAD_LOCAL_STORAGE) + /* Grab the TLS pointer */ + ldr r4, =_thread_offset_to_tls + adds r4, r2, r4 + ldr r0, [r4] + +#if defined(CONFIG_CPU_CORTEX_R) + /* Store TLS pointer in the "Process ID" register. + * This register is used as a base pointer to all + * thread variables with offsets added by toolchain. + */ + mcr 15, 0, r0, cr13, cr0, 3 +#endif +#endif + /* Restore previous interrupt disable state (irq_lock key) * (We clear the arch.basepri field after restoring state) */ diff --git a/include/arch/arm/aarch32/cortex_a_r/scripts/linker.ld b/include/arch/arm/aarch32/cortex_a_r/scripts/linker.ld index c3f5a3d9348..def88f5a99b 100644 --- a/include/arch/arm/aarch32/cortex_a_r/scripts/linker.ld +++ b/include/arch/arm/aarch32/cortex_a_r/scripts/linker.ld @@ -174,6 +174,7 @@ SECTIONS _image_rodata_start = .; #include +#include SECTION_PROLOGUE(_RODATA_SECTION_NAME,,) {