soc: renesas: Add support for Renesas RZ/A2M

Add support for Renesas RZ/A2M

Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>

soc/renesas/rz/rza2m/CMakeLists.txt

@@ -0,0 +1,15 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(
+  soc.c
+  ../common/loader_program.S
+)
+
+zephyr_library_sources_ifdef(CONFIG_ARM_AARCH32_MMU mmu_regions.c)
+
+zephyr_include_directories(.)
+
+zephyr_linker_sources(SECTIONS sections.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "")

soc/renesas/rz/rza2m/Kconfig

@@ -0,0 +1,6 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RZA2M
+	select ARM
+	select CPU_CORTEX_A9

soc/renesas/rz/rza2m/Kconfig.defconfig

@@ -0,0 +1,28 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RZA2M
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/soc/cpg/p1clk,clock-frequency)
+
+config NUM_IRQS
+	default 512
+
+config FLASH_SIZE
+	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
+
+config FLASH_BASE_ADDRESS
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
+
+DT_CHOSEN_IMAGE_ZEPHYR = zephyr,code-partition
+DT_CHOSEN_Z_SRAM = zephyr,sram
+
+config BUILD_OUTPUT_ADJUST_LMA
+	default "($(dt_chosen_partition_addr_hex,$(DT_CHOSEN_IMAGE_ZEPHYR)) - \
+	$(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_SRAM)))"
+
+config BUILD_OUTPUT_ADJUST_LMA_SECTIONS
+	default "*;!.loader"
+
+endif # SOC_SERIES_RZA2M

soc/renesas/rz/rza2m/Kconfig.soc

@@ -0,0 +1,24 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RZA2M
+	bool
+	select SOC_FAMILY_RENESAS_RZ
+	help
+	  Renesas RZ/A2M series
+
+config SOC_SERIES
+	default "rza2m" if SOC_SERIES_RZA2M
+
+config SOC_R7S921053VCBG
+	bool
+	select SOC_SERIES_RZA2M
+	help
+	  R7S921053VCBG
+
+config SOC_R7S921053VCBG_CA9
+	bool
+	select SOC_R7S921053VCBG
+
+config SOC
+	default "r7s921053vcbg" if SOC_R7S921053VCBG

soc/renesas/rz/rza2m/mmu_regions.c

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/sys/util.h>
+#include <zephyr/arch/arm/mmu/arm_mmu.h>
+#include <zephyr/devicetree.h>
+
+extern char _vector_start[];
+
+static const struct arm_mmu_region mmu_regions[] = {
+	MMU_REGION_FLAT_ENTRY("vector_tables", POINTER_TO_UINT(_vector_start), 0x1000,
+			      MT_STRONGLY_ORDERED | MPERM_R | MPERM_X),
+
+	MMU_REGION_FLAT_ENTRY("pl310", 0x1F003000, 0x1000,
+			      MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
+
+	MMU_REGION_FLAT_ENTRY("gic", DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
+			      DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
+			      MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
+
+	MMU_REGION_FLAT_ENTRY("gic", DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1),
+			      DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1),
+			      MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
+};
+
+const struct arm_mmu_config mmu_config = {
+	.num_regions = ARRAY_SIZE(mmu_regions),
+	.mmu_regions = mmu_regions,
+};

soc/renesas/rz/rza2m/sections.ld

@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/devicetree.h>
+
+SECTION_PROLOGUE(.loader, CONFIG_FLASH_BASE_ADDRESS,)
+{
+	__loader_program_start = .;
+	KEEP(*(.loader_text.*))
+	__loader_program_end = .;
+} GROUP_LINK_IN(FLASH)

soc/renesas/rz/rza2m/soc.c

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/init.h>
+#include <zephyr/arch/cpu.h>
+#include <zephyr/kernel.h>
+
+extern char _vector_start[];
+
+void relocate_vector_table(void)
+{
+#if defined(CONFIG_XIP) && (CONFIG_FLASH_BASE_ADDRESS != 0) ||                                     \
+	!defined(CONFIG_XIP) && (CONFIG_SRAM_BASE_ADDRESS != 0)
+	write_sctlr(read_sctlr() & ~HIVECS);
+#elif defined(CONFIG_SW_VECTOR_RELAY) || defined(CONFIG_SW_VECTOR_RELAY_CLIENT)
+	_vector_table_pointer = _vector_start;
+#endif
+	__set_VBAR(POINTER_TO_UINT(_vector_start));
+}

soc/renesas/rz/rza2m/soc.h

@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RZA2M_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RZA2M_SOC_H_
+
+/*
+ * The following definitions are required for the inclusion of the CMSIS
+ * Common Peripheral Access Layer for aarch32 Cortex-A CPUs:
+ */
+
+#define __CORTEX_A 9U
+
+#endif /* ZEPHYR_SOC_RENESAS_RZA2M_SOC_H_ */

soc/renesas/rz/soc.yml

@@ -1,6 +1,9 @@
 family:
   - name: renesas_rz
     series:
+      - name: rza2m
+        socs:
+          - name: r7s921053vcbg
       - name: rza3ul
         socs:
           - name: r9a07g063u02gbg