diff --git a/dts/arm/renesas/rz/rza/r7s9210.dtsi b/dts/arm/renesas/rz/rza/r7s9210.dtsi new file mode 100644 index 00000000000..ff25829605d --- /dev/null +++ b/dts/arm/renesas/rz/rza/r7s9210.dtsi @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +/ { + compatible = "renesas,r7s9210"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + }; + + osc: osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gic: interrupt-controller@e8221000 { + compatible = "arm,gic-400", "arm,gic-v2", "arm,gic"; + #interrupt-cells = <4>; + #address-cells = <0>; + interrupt-controller; + reg = <0xe8221000 0x1000>, + <0xe8222000 0x1000>; + }; + + ram: memory@80020000 { + compatible = "mmio-sram"; + reg = <0x80020000 (DT_SIZE_M(4) - 0x20000)>; + }; + }; +}; diff --git a/soc/renesas/rz/rza2m/CMakeLists.txt b/soc/renesas/rz/rza2m/CMakeLists.txt new file mode 100644 index 00000000000..d968c2bd475 --- /dev/null +++ b/soc/renesas/rz/rza2m/CMakeLists.txt @@ -0,0 +1,15 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + soc.c + ../common/loader_program.S +) + +zephyr_library_sources_ifdef(CONFIG_ARM_AARCH32_MMU mmu_regions.c) + +zephyr_include_directories(.) + +zephyr_linker_sources(SECTIONS sections.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/rz/rza2m/Kconfig b/soc/renesas/rz/rza2m/Kconfig new file mode 100644 index 00000000000..7b81cc9c2da --- /dev/null +++ b/soc/renesas/rz/rza2m/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RZA2M + select ARM + select CPU_CORTEX_A9 diff --git a/soc/renesas/rz/rza2m/Kconfig.defconfig b/soc/renesas/rz/rza2m/Kconfig.defconfig new file mode 100644 index 00000000000..31f95051d85 --- /dev/null +++ b/soc/renesas/rz/rza2m/Kconfig.defconfig @@ -0,0 +1,28 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RZA2M + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/soc/cpg/p1clk,clock-frequency) + +config NUM_IRQS + default 512 + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +DT_CHOSEN_IMAGE_ZEPHYR = zephyr,code-partition +DT_CHOSEN_Z_SRAM = zephyr,sram + +config BUILD_OUTPUT_ADJUST_LMA + default "($(dt_chosen_partition_addr_hex,$(DT_CHOSEN_IMAGE_ZEPHYR)) - \ + $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_SRAM)))" + +config BUILD_OUTPUT_ADJUST_LMA_SECTIONS + default "*;!.loader" + +endif # SOC_SERIES_RZA2M diff --git a/soc/renesas/rz/rza2m/Kconfig.soc b/soc/renesas/rz/rza2m/Kconfig.soc new file mode 100644 index 00000000000..c2897950bb0 --- /dev/null +++ b/soc/renesas/rz/rza2m/Kconfig.soc @@ -0,0 +1,24 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RZA2M + bool + select SOC_FAMILY_RENESAS_RZ + help + Renesas RZ/A2M series + +config SOC_SERIES + default "rza2m" if SOC_SERIES_RZA2M + +config SOC_R7S921053VCBG + bool + select SOC_SERIES_RZA2M + help + R7S921053VCBG + +config SOC_R7S921053VCBG_CA9 + bool + select SOC_R7S921053VCBG + +config SOC + default "r7s921053vcbg" if SOC_R7S921053VCBG diff --git a/soc/renesas/rz/rza2m/mmu_regions.c b/soc/renesas/rz/rza2m/mmu_regions.c new file mode 100644 index 00000000000..483ba009c8f --- /dev/null +++ b/soc/renesas/rz/rza2m/mmu_regions.c @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +extern char _vector_start[]; + +static const struct arm_mmu_region mmu_regions[] = { + MMU_REGION_FLAT_ENTRY("vector_tables", POINTER_TO_UINT(_vector_start), 0x1000, + MT_STRONGLY_ORDERED | MPERM_R | MPERM_X), + + MMU_REGION_FLAT_ENTRY("pl310", 0x1F003000, 0x1000, + MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W), + + MMU_REGION_FLAT_ENTRY("gic", DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0), + DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0), + MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W), + + MMU_REGION_FLAT_ENTRY("gic", DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1), + DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1), + MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W), +}; + +const struct arm_mmu_config mmu_config = { + .num_regions = ARRAY_SIZE(mmu_regions), + .mmu_regions = mmu_regions, +}; diff --git a/soc/renesas/rz/rza2m/sections.ld b/soc/renesas/rz/rza2m/sections.ld new file mode 100644 index 00000000000..3abeb09abe3 --- /dev/null +++ b/soc/renesas/rz/rza2m/sections.ld @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include + +SECTION_PROLOGUE(.loader, CONFIG_FLASH_BASE_ADDRESS,) +{ + __loader_program_start = .; + KEEP(*(.loader_text.*)) + __loader_program_end = .; +} GROUP_LINK_IN(FLASH) diff --git a/soc/renesas/rz/rza2m/soc.c b/soc/renesas/rz/rza2m/soc.c new file mode 100644 index 00000000000..a48668181f6 --- /dev/null +++ b/soc/renesas/rz/rza2m/soc.c @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +extern char _vector_start[]; + +void relocate_vector_table(void) +{ +#if defined(CONFIG_XIP) && (CONFIG_FLASH_BASE_ADDRESS != 0) || \ + !defined(CONFIG_XIP) && (CONFIG_SRAM_BASE_ADDRESS != 0) + write_sctlr(read_sctlr() & ~HIVECS); +#elif defined(CONFIG_SW_VECTOR_RELAY) || defined(CONFIG_SW_VECTOR_RELAY_CLIENT) + _vector_table_pointer = _vector_start; +#endif + __set_VBAR(POINTER_TO_UINT(_vector_start)); +} diff --git a/soc/renesas/rz/rza2m/soc.h b/soc/renesas/rz/rza2m/soc.h new file mode 100644 index 00000000000..c58c8ec84bf --- /dev/null +++ b/soc/renesas/rz/rza2m/soc.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_RENESAS_RZA2M_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RZA2M_SOC_H_ + +/* + * The following definitions are required for the inclusion of the CMSIS + * Common Peripheral Access Layer for aarch32 Cortex-A CPUs: + */ + +#define __CORTEX_A 9U + +#endif /* ZEPHYR_SOC_RENESAS_RZA2M_SOC_H_ */ diff --git a/soc/renesas/rz/soc.yml b/soc/renesas/rz/soc.yml index 9d831dc8b07..57681f2cab3 100644 --- a/soc/renesas/rz/soc.yml +++ b/soc/renesas/rz/soc.yml @@ -1,6 +1,9 @@ family: - name: renesas_rz series: + - name: rza2m + socs: + - name: r7s921053vcbg - name: rza3ul socs: - name: r9a07g063u02gbg