diff --git a/arch/arm/soc/st_stm32/stm32f1/soc.h b/arch/arm/soc/st_stm32/stm32f1/soc.h
index b277095b96d..628e2752657 100644
--- a/arch/arm/soc/st_stm32/stm32f1/soc.h
+++ b/arch/arm/soc/st_stm32/stm32f1/soc.h
@@ -30,7 +30,12 @@
 
 #include <stm32f1xx.h>
 
-/* IO pin functions */
+/* IO pin functions are mostly common across STM32 devices. Notable
+ * exception is STM32F1 as these MCUs do not have registers for
+ * configuration of pin's alternate function. The configuration is
+ * done implicitly by setting specific mode and config in MODE and CNF
+ * registers for particular pin.
+ */
 enum stm32f10x_pin_config_mode {
 	STM32F10X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
 	STM32F10X_PIN_CONFIG_BIAS_PULL_UP,
diff --git a/drivers/pinmux/stm32/pinmux_stm32.c b/drivers/pinmux/stm32/pinmux_stm32.c
index b8c2dd44f2c..10d953b32e4 100644
--- a/drivers/pinmux/stm32/pinmux_stm32.c
+++ b/drivers/pinmux/stm32/pinmux_stm32.c
@@ -51,12 +51,7 @@ static int enable_port(uint32_t port, struct device *clk)
 	}
 
 	/* TODO: Merge this and move the port clock to the soc file */
-#if defined(CONFIG_SOC_SERIES_STM32F1X) || defined(CONFIG_SOC_SERIES_STM32L4X)
-	clock_control_subsys_t subsys = stm32_get_port_clock(port);
-
-	return clock_control_on(clk, subsys);
-
-#elif CONFIG_SOC_SERIES_STM32F4X
+#ifdef	CONFIG_SOC_SERIES_STM32F4X
 	struct stm32f4x_pclken pclken;
 
 	/* AHB1 bus for all the GPIO ports */
@@ -64,6 +59,11 @@ static int enable_port(uint32_t port, struct device *clk)
 	pclken.enr = ports_enable[port];
 
 	return clock_control_on(clk, (clock_control_subsys_t *) &pclken);
+
+#else /* SOC_SERIES_STM32F1X || SOC_SERIES_STM32F3X || SOC_SERIES_STM32L4X */
+	clock_control_subsys_t subsys = stm32_get_port_clock(port);
+
+	return clock_control_on(clk, subsys);
 #endif
 }