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spi: sam: Specify pinmux for chipselect via Kconfig

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Move to using Kconfig (like other Atmel SAM drivers do) to specify the
pinmux setting for SAMe70 SoCs.  Updated the sam_e70_xplained board to
set the default in Kconfig.defconfig instead of via board.h

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2018-11-13 08:11:27 -06:00 • committed by Kumar Gala
commit 71c3dd11c5
5 changed files with 160 additions and 23 deletions
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36
soc/arm/atmel_sam/same70/soc_pinmap.h
View file

@ -137,23 +137,47 @@
/* Serial Peripheral Interface (SPI) */
#define PIN_SPI0_CS0_PB2 {PIO_PB2D_SPI0_NPCS0, PIOB, ID_PIOB, SOC_GPIO_FUNC_D}
#define PIN_SPI0_CS1_PA31 {PIO_PA31A_SPI0_NPCS1, PIOA, ID_PIOA, SOC_GPIO_FUNC_A}
#define PIN_SPI0_CS1_PD25 {PIO_PD25B_SPI0_NPCS1, PIOD, ID_PIOD, SOC_GPIO_FUNC_B}
#define PIN_SPI0_CS2_PD12 {PIO_PD12C_SPI0_NPCS2, PIOD, ID_PIOD, SOC_GPIO_FUNC_C}
#define PIN_SPI0_CS3_PD27 {PIO_PD27B_SPI0_NPCS3, PIOD, ID_PIOD, SOC_GPIO_FUNC_B}
#ifdef CONFIG_SPI_SAME70_PORT_0_PIN_CS0
#define PIN_SPI0_CS0 {PIO_PB2D_SPI0_NPCS0, PIOB, ID_PIOB, SOC_GPIO_FUNC_D}
#endif
#ifdef CONFIG_SPI_SAME70_PORT_0_PIN_CS1_PA31
#define PIN_SPI0_CS1 {PIO_PA31A_SPI0_NPCS1, PIOA, ID_PIOA, SOC_GPIO_FUNC_A}
#endif
#ifdef CONFIG_SPI_SAME70_PORT_0_PIN_CS1_PD25
#define PIN_SPI0_CS1 {PIO_PD25B_SPI0_NPCS1, PIOD, ID_PIOD, SOC_GPIO_FUNC_B}
#endif
#ifdef CONFIG_SPI_SAME70_PORT_0_PIN_CS2
#define PIN_SPI0_CS2 {PIO_PD12C_SPI0_NPCS2, PIOD, ID_PIOD, SOC_GPIO_FUNC_C}
#endif
#ifdef CONFIG_SPI_SAME70_PORT_0_PIN_CS3
#define PIN_SPI0_CS3 {PIO_PD27B_SPI0_NPCS3, PIOD, ID_PIOD, SOC_GPIO_FUNC_B}
#endif
#define PINS_SPI0_MASK \
(PIO_PD20B_SPI0_MISO | PIO_PD21B_SPI0_MOSI | PIO_PD22B_SPI0_SPCK)
#define PINS_SPI0 {PINS_SPI0_MASK, PIOD, ID_PIOD, SOC_GPIO_FUNC_B}
#define PIN_SPI1_CS0_PC25 {PIO_PC25C_SPI1_NPCS0, PIOC, ID_PIOC, SOC_GPIO_FUNC_C}
#ifdef CONFIG_SPI_SAME70_PORT_0_PIN_CS0
#define PIN_SPI1_CS0 {PIO_PC25C_SPI1_NPCS0, PIOC, ID_PIOC, SOC_GPIO_FUNC_C}
#endif
#ifdef CONFIG_SPI_SAME70_PORT_1_PIN_CS1_PC28
#define PIN_SPI1_CS1_PC28 {PIO_PC28C_SPI1_NPCS1, PIOC, ID_PIOC, SOC_GPIO_FUNC_C}
#endif
#ifdef CONFIG_SPI_SAME70_PORT_1_PIN_CS1_PD0
#define PIN_SPI1_CS1_PD0 {PIO_PD0C_SPI1_NPCS1, PIOD, ID_PIOD, SOC_GPIO_FUNC_C}
#endif
#ifdef CONFIG_SPI_SAME70_PORT_1_PIN_CS2_PC29
#define PIN_SPI1_CS2_PC29 {PIO_PC29C_SPI1_NPCS2, PIOC, ID_PIOC, SOC_GPIO_FUNC_C}
#endif
#ifdef CONFIG_SPI_SAME70_PORT_1_PIN_CS2_PD1
#define PIN_SPI1_CS2_PD1 {PIO_PD1C_SPI1_NPCS2, PIOD, ID_PIOD, SOC_GPIO_FUNC_C}
#endif
#ifdef CONFIG_SPI_SAME70_PORT_1_PIN_CS3_PC30
#define PIN_SPI1_CS3_PC30 {PIO_PC30C_SPI1_NPCS3, PIOC, ID_PIOC, SOC_GPIO_FUNC_C}
#endif
#ifdef CONFIG_SPI_SAME70_PORT_1_PIN_CS3_PD2
#define PIN_SPI1_CS3_PD2 {PIO_PD2C_SPI1_NPCS3, PIOD, ID_PIOD, SOC_GPIO_FUNC_C}
#endif
#define PINS_SPI1_MASK \
(PIO_PC26C_SPI1_MISO | PIO_PC27C_SPI1_MOSI | PIO_PC24C_SPI1_SPCK)