From 71c3dd11c5302fbb05144322a382c24d45621f14 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 13 Nov 2018 08:11:27 -0600 Subject: [PATCH] spi: sam: Specify pinmux for chipselect via Kconfig Move to using Kconfig (like other Atmel SAM drivers do) to specify the pinmux setting for SAMe70 SoCs. Updated the sam_e70_xplained board to set the default in Kconfig.defconfig instead of via board.h Signed-off-by: Kumar Gala --- boards/arm/sam_e70_xplained/Kconfig.defconfig | 11 +++ boards/arm/sam_e70_xplained/board.h | 12 --- drivers/spi/Kconfig.sam | 87 +++++++++++++++++++ drivers/spi/spi_sam.c | 37 ++++++-- soc/arm/atmel_sam/same70/soc_pinmap.h | 36 ++++++-- 5 files changed, 160 insertions(+), 23 deletions(-) delete mode 100644 boards/arm/sam_e70_xplained/board.h diff --git a/boards/arm/sam_e70_xplained/Kconfig.defconfig b/boards/arm/sam_e70_xplained/Kconfig.defconfig index 2f343067a5b..41fe88a0480 100644 --- a/boards/arm/sam_e70_xplained/Kconfig.defconfig +++ b/boards/arm/sam_e70_xplained/Kconfig.defconfig @@ -66,4 +66,15 @@ config ETH_SAM_GMAC endif # NETWORKING +if SPI + +if SPI_SAM_PORT_0 + +config SPI_SAME70_PORT_0_PIN_CS3 + def_bool y + +endif # SPI_SAM_PORT_0 + +endif # SPI + endif # BOARD_SAM_E70_XPLAINED diff --git a/boards/arm/sam_e70_xplained/board.h b/boards/arm/sam_e70_xplained/board.h deleted file mode 100644 index 5a2aa5f1867..00000000000 --- a/boards/arm/sam_e70_xplained/board.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (c) 2018 Justin Watson - * Copyright (c) 2016 Piotr Mienkowski - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _INC_BOARD_H_ -#define _INC_BOARD_H_ - -#define PINS_SPI0_CS {PIN_SPI0_CS3_PD27} - -#endif /* _INC_BOARD_H_ */ diff --git a/drivers/spi/Kconfig.sam b/drivers/spi/Kconfig.sam index 179f326eedd..a68df6d15b3 100644 --- a/drivers/spi/Kconfig.sam +++ b/drivers/spi/Kconfig.sam @@ -9,3 +9,90 @@ menuconfig SPI_SAM select HAS_DTS_SPI help Enable support for the SAM SPI driver. + +config SPI_SAM_PORT_0 + bool "Enable SPI0" + depends on SPI_SAM + help + Enable SPI0 at boot + +if SPI_SAM_PORT_0 + +config SPI_SAME70_PORT_0_PIN_CS0 + bool "CS0 pin" + depends on SOC_SERIES_SAME70 + +choice SPI_SAME70_PORT_0_PIN_CS1 + bool "CS1 pin" + optional + depends on SOC_SERIES_SAME70 + + config SPI_SAME70_PORT_0_PIN_CS1_PA31 + bool "PA31" + + config SPI_SAME70_PORT_0_PIN_CS1_PD25 + bool "PD25" + +endchoice + +config SPI_SAME70_PORT_0_PIN_CS2 + bool "CS2 pin" + depends on SOC_SERIES_SAME70 + +config SPI_SAME70_PORT_0_PIN_CS3 + bool "CS3 pin" + depends on SOC_SERIES_SAME70 + +endif # SPI_SAM_PORT_0 + +config SPI_SAM_PORT_1 + bool "Enable SPI1" + depends on SPI_SAM + help + Enable SPI1 at boot + +if SPI_SAM_PORT_1 + +config SPI_SAME70_PORT_1_PIN_CS0 + bool "CS0 pin" + depends on SOC_SERIES_SAME70 + +choice SPI_SAME70_PORT_1_PIN_CS1 + prompt "CS1 pin" + optional + depends on SOC_SERIES_SAME70 + + config SPI_SAME70_PORT_1_PIN_CS1_PC28 + bool "PC28" + + config SPI_SAME70_PORT_1_PIN_CS1_PD0 + bool "PD0" + +endchoice + +choice SPI_SAME70_PORT_1_PIN_CS2 + prompt "CS2 pin" + optional + depends on SOC_SERIES_SAME70 + + config SPI_SAME70_PORT_1_PIN_CS2_PC29 + bool "PC29" + + config SPI_SAME70_PORT_1_PIN_CS2_PD1 + bool "PD1" + +endchoice + +choice SPI_SAME70_PORT_1_PIN_CS3 + prompt "CS3 pin" + optional + depends on SOC_SERIES_SAME70 + + config SPI_SAME70_PORT_1_PIN_CS3_PC30 + bool "PC30" + + config SPI_SAME70_PORT_1_PIN_CS3_PD2 + bool "PD2" + +endchoice +endif # SPI_SAM_PORT_1 diff --git a/drivers/spi/spi_sam.c b/drivers/spi/spi_sam.c index c1b0bfca6ef..e477a946c59 100644 --- a/drivers/spi/spi_sam.c +++ b/drivers/spi/spi_sam.c @@ -14,7 +14,6 @@ LOG_MODULE_REGISTER(spi_sam); #include #include #include -#include #define SAM_SPI_CHIP_SELECT_COUNT 4 @@ -442,14 +441,42 @@ static const struct spi_driver_api spi_sam_driver_api = { .release = spi_sam_release, }; -#ifndef PINS_SPI0_CS -#define PINS_SPI0_CS { {0, (Pio *)0, 0, 0}, } +#ifndef PIN_SPI0_CS0 +#define PIN_SPI0_CS0 {0, (Pio *)0, 0, 0} #endif -#ifndef PINS_SPI1_CS -#define PINS_SPI1_CS { {0, (Pio *)0, 0, 0}, } +#ifndef PIN_SPI0_CS1 +#define PIN_SPI0_CS1 {0, (Pio *)0, 0, 0} #endif +#ifndef PIN_SPI0_CS2 +#define PIN_SPI0_CS2 {0, (Pio *)0, 0, 0} +#endif + +#ifndef PIN_SPI0_CS3 +#define PIN_SPI0_CS3 {0, (Pio *)0, 0, 0} +#endif + +#define PINS_SPI0_CS { PIN_SPI0_CS0, PIN_SPI0_CS1, PIN_SPI0_CS2, PIN_SPI0_CS3 } + +#ifndef PIN_SPI1_CS0 +#define PIN_SPI1_CS0 {0, (Pio *)0, 0, 0} +#endif + +#ifndef PIN_SPI1_CS1 +#define PIN_SPI1_CS1 {0, (Pio *)0, 0, 0} +#endif + +#ifndef PIN_SPI1_CS2 +#define PIN_SPI1_CS2 {0, (Pio *)0, 0, 0} +#endif + +#ifndef PIN_SPI1_CS3 +#define PIN_SPI1_CS3 {0, (Pio *)0, 0, 0} +#endif + +#define PINS_SPI1_CS { PIN_SPI1_CS0, PIN_SPI1_CS1, PIN_SPI1_CS2, PIN_SPI1_CS3 } + #define SPI_SAM_DEFINE_CONFIG(n) \ static const struct spi_sam_config spi_sam_config_##n = { \ .regs = (Spi *)DT_SPI_##n##_BASE_ADDRESS, \ diff --git a/soc/arm/atmel_sam/same70/soc_pinmap.h b/soc/arm/atmel_sam/same70/soc_pinmap.h index d19c43d043b..34c0c54272e 100644 --- a/soc/arm/atmel_sam/same70/soc_pinmap.h +++ b/soc/arm/atmel_sam/same70/soc_pinmap.h @@ -137,23 +137,47 @@ /* Serial Peripheral Interface (SPI) */ -#define PIN_SPI0_CS0_PB2 {PIO_PB2D_SPI0_NPCS0, PIOB, ID_PIOB, SOC_GPIO_FUNC_D} -#define PIN_SPI0_CS1_PA31 {PIO_PA31A_SPI0_NPCS1, PIOA, ID_PIOA, SOC_GPIO_FUNC_A} -#define PIN_SPI0_CS1_PD25 {PIO_PD25B_SPI0_NPCS1, PIOD, ID_PIOD, SOC_GPIO_FUNC_B} -#define PIN_SPI0_CS2_PD12 {PIO_PD12C_SPI0_NPCS2, PIOD, ID_PIOD, SOC_GPIO_FUNC_C} -#define PIN_SPI0_CS3_PD27 {PIO_PD27B_SPI0_NPCS3, PIOD, ID_PIOD, SOC_GPIO_FUNC_B} +#ifdef CONFIG_SPI_SAME70_PORT_0_PIN_CS0 +#define PIN_SPI0_CS0 {PIO_PB2D_SPI0_NPCS0, PIOB, ID_PIOB, SOC_GPIO_FUNC_D} +#endif +#ifdef CONFIG_SPI_SAME70_PORT_0_PIN_CS1_PA31 +#define PIN_SPI0_CS1 {PIO_PA31A_SPI0_NPCS1, PIOA, ID_PIOA, SOC_GPIO_FUNC_A} +#endif +#ifdef CONFIG_SPI_SAME70_PORT_0_PIN_CS1_PD25 +#define PIN_SPI0_CS1 {PIO_PD25B_SPI0_NPCS1, PIOD, ID_PIOD, SOC_GPIO_FUNC_B} +#endif +#ifdef CONFIG_SPI_SAME70_PORT_0_PIN_CS2 +#define PIN_SPI0_CS2 {PIO_PD12C_SPI0_NPCS2, PIOD, ID_PIOD, SOC_GPIO_FUNC_C} +#endif +#ifdef CONFIG_SPI_SAME70_PORT_0_PIN_CS3 +#define PIN_SPI0_CS3 {PIO_PD27B_SPI0_NPCS3, PIOD, ID_PIOD, SOC_GPIO_FUNC_B} +#endif #define PINS_SPI0_MASK \ (PIO_PD20B_SPI0_MISO | PIO_PD21B_SPI0_MOSI | PIO_PD22B_SPI0_SPCK) #define PINS_SPI0 {PINS_SPI0_MASK, PIOD, ID_PIOD, SOC_GPIO_FUNC_B} -#define PIN_SPI1_CS0_PC25 {PIO_PC25C_SPI1_NPCS0, PIOC, ID_PIOC, SOC_GPIO_FUNC_C} +#ifdef CONFIG_SPI_SAME70_PORT_0_PIN_CS0 +#define PIN_SPI1_CS0 {PIO_PC25C_SPI1_NPCS0, PIOC, ID_PIOC, SOC_GPIO_FUNC_C} +#endif +#ifdef CONFIG_SPI_SAME70_PORT_1_PIN_CS1_PC28 #define PIN_SPI1_CS1_PC28 {PIO_PC28C_SPI1_NPCS1, PIOC, ID_PIOC, SOC_GPIO_FUNC_C} +#endif +#ifdef CONFIG_SPI_SAME70_PORT_1_PIN_CS1_PD0 #define PIN_SPI1_CS1_PD0 {PIO_PD0C_SPI1_NPCS1, PIOD, ID_PIOD, SOC_GPIO_FUNC_C} +#endif +#ifdef CONFIG_SPI_SAME70_PORT_1_PIN_CS2_PC29 #define PIN_SPI1_CS2_PC29 {PIO_PC29C_SPI1_NPCS2, PIOC, ID_PIOC, SOC_GPIO_FUNC_C} +#endif +#ifdef CONFIG_SPI_SAME70_PORT_1_PIN_CS2_PD1 #define PIN_SPI1_CS2_PD1 {PIO_PD1C_SPI1_NPCS2, PIOD, ID_PIOD, SOC_GPIO_FUNC_C} +#endif +#ifdef CONFIG_SPI_SAME70_PORT_1_PIN_CS3_PC30 #define PIN_SPI1_CS3_PC30 {PIO_PC30C_SPI1_NPCS3, PIOC, ID_PIOC, SOC_GPIO_FUNC_C} +#endif +#ifdef CONFIG_SPI_SAME70_PORT_1_PIN_CS3_PD2 #define PIN_SPI1_CS3_PD2 {PIO_PD2C_SPI1_NPCS3, PIOD, ID_PIOD, SOC_GPIO_FUNC_C} +#endif #define PINS_SPI1_MASK \ (PIO_PC26C_SPI1_MISO | PIO_PC27C_SPI1_MOSI | PIO_PC24C_SPI1_SPCK)