arch: arm: core: aarch32: introduce basic ARMv7 MMU support
An initial implementation for memory management using the ARMv7 MMU. A single L1 translation table for the whole 4 GB address space is al- ways present, a configurable number of L2 page tables are linked to the L1 table based on the static memory area configuration at boot time, or whenever arch_mem_map/arch_mem_unmap are called at run-time. Currently, a CPU with the Multiprocessor Extensions and execution at PL1 are always assumed. Userspace-related features or thread stack guard pages are not yet supported. Neither are LPAE, PXN or TEX re- mapping. All mappings are currently assigned to the same domain. Re- garding the permissions model, access permissions are specified using the AP[2:1] model rather than the older AP[2:0] model, which, accor- ding to ARM's documentation, is deprecated and should no longer be used. The newer model adds some complexity when it comes to mapping pages as unaccessible (the AP[2:1] model doesn't support explicit specification of "no R, no W" permissions, it's always at least "RO"), this is accomplished by invalidating the ID bits of the respective page's PTE. Includes sources, Kconfig integration, adjusted CMakeLists and the modified linker command file (proper section alignment!). Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
This commit is contained in:
Immo Birnbaum
Carles Cufí
parent
eac90eeb52
commit
70c403c215
10 changed files with 1475 additions and 2 deletions
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@ -71,6 +71,8 @@ extern "C" {
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*/
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#if defined(CONFIG_USERSPACE)
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#define Z_THREAD_MIN_STACK_ALIGN CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE
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#elif defined(CONFIG_ARM_MMU)
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#define Z_THREAD_MIN_STACK_ALIGN CONFIG_ARM_MMU_REGION_MIN_ALIGN_AND_SIZE
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#else
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#define Z_THREAD_MIN_STACK_ALIGN ARCH_STACK_PTR_ALIGN
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#endif
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@ -190,6 +192,9 @@ extern "C" {
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#include <arch/arm/aarch32/mpu/nxp_mpu.h>
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#endif /* CONFIG_CPU_HAS_NXP_MPU */
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#endif /* CONFIG_ARM_MPU */
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#ifdef CONFIG_ARM_AARCH32_MMU
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#include <arch/arm/aarch32/mmu/arm_mmu.h>
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#endif /* CONFIG_ARM_AARCH32_MMU */
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#ifdef __cplusplus
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}
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@ -58,6 +58,8 @@
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*/
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#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)
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_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;
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#elif defined(CONFIG_ARM_AARCH32_MMU)
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_region_min_align = CONFIG_MMU_PAGE_SIZE;
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#else
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/* If building without MPU support, use default 4-byte alignment. */
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_region_min_align = 4;
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@ -72,6 +74,8 @@ _region_min_align = 4;
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. = ALIGN(_region_min_align)
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#endif
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#define BSS_ALIGN ALIGN(_region_min_align)
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MEMORY
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{
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FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE
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@ -127,7 +131,11 @@ SECTIONS
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SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)
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{
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. = ALIGN(_region_min_align);
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__text_region_start = .;
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#ifndef CONFIG_XIP
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z_mapped_start = .;
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#endif
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#include <linker/kobject-text.ld>
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@ -144,6 +152,7 @@ SECTIONS
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} GROUP_LINK_IN(ROMABLE_REGION)
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__text_region_end = .;
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. = ALIGN(_region_min_align);
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#if defined (CONFIG_CPLUSPLUS)
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SECTION_PROLOGUE(.ARM.extab,,)
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@ -170,6 +179,7 @@ SECTIONS
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__exidx_end = .;
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} GROUP_LINK_IN(ROMABLE_REGION)
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. = ALIGN(_region_min_align);
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__rodata_region_start = .;
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#include <linker/common-rom.ld>
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@ -210,6 +220,7 @@ SECTIONS
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__rodata_region_end = .;
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__rom_region_end = .;
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MPU_ALIGN(__rodata_region_end - __rom_region_start);
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_image_rom_end_order = (LOG2CEIL(__rom_region_end) - 1) << 1;
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GROUP_END(ROMABLE_REGION)
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@ -234,6 +245,9 @@ SECTIONS
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*/
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. = ALIGN(_region_min_align);
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_image_ram_start = .;
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#ifdef CONFIG_XIP
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z_mapped_start = .;
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#endif
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/* Located in generated directory. This file is populated by the
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* zephyr_linker_sources() Cmake function.
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@ -250,7 +264,7 @@ SECTIONS
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_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);
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#endif /* CONFIG_USERSPACE */
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SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
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SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD), BSS_ALIGN)
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{
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/*
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* For performance, BSS section is assumed to be 4 byte aligned and
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@ -316,8 +330,10 @@ SECTIONS
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/* Define linker symbols */
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. = ALIGN(_region_min_align);
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_image_ram_end = .;
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_end = .; /* end of image */
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z_mapped_end = .;
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__kernel_ram_end = RAM_ADDR + RAM_SIZE;
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__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;
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105
include/arch/arm/aarch32/mmu/arm_mmu.h
Normal file
105
include/arch/arm/aarch32/mmu/arm_mmu.h
Normal file
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@ -0,0 +1,105 @@
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/*
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* ARMv7 MMU support
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*
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* Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_AARCH32_ARM_MMU_H_
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#define ZEPHYR_INCLUDE_ARCH_AARCH32_ARM_MMU_H_
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#ifndef _ASMLANGUAGE
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/*
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* Comp.:
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* ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition,
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* ARM document ID DDI0406C Rev. d, March 2018
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* Memory type definitions:
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* Table B3-10, chap. B3.8.2, p. B3-1363f.
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* Outer / inner cache attributes for cacheable memory:
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* Table B3-11, chap. B3.8.2, p. B3-1364
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*/
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/*
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* The following definitions are used when specifying a memory
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* range to be mapped at boot time using the MMU_REGION_ENTRY
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* macro.
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*/
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#define MT_STRONGLY_ORDERED BIT(0)
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#define MT_DEVICE BIT(1)
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#define MT_NORMAL BIT(2)
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#define MT_MASK 0x7
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#define MPERM_R BIT(3)
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#define MPERM_W BIT(4)
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#define MPERM_X BIT(5)
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#define MPERM_UNPRIVILEGED BIT(6)
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#define MATTR_NON_SECURE BIT(7)
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#define MATTR_NON_GLOBAL BIT(8)
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#define MATTR_SHARED BIT(9)
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#define MATTR_CACHE_OUTER_WB_WA BIT(10)
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#define MATTR_CACHE_OUTER_WT_nWA BIT(11)
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#define MATTR_CACHE_OUTER_WB_nWA BIT(12)
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#define MATTR_CACHE_INNER_WB_WA BIT(13)
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#define MATTR_CACHE_INNER_WT_nWA BIT(14)
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#define MATTR_CACHE_INNER_WB_nWA BIT(15)
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#define MATTR_MAY_MAP_L1_SECTION BIT(16)
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/*
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* The following macros are used for adding constant entries
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* mmu_regions array of the mmu_config struct. Use MMU_REGION_ENTRY
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* for the specification of mappings whose PA and VA differ,
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* the use of MMU_REGION_FLAT_ENTRY always results in an identity
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* mapping, which are used for the mappings of the Zephyr image's
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* code and data.
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*/
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#define MMU_REGION_ENTRY(_name, _base_pa, _base_va, _size, _attrs) \
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{\
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.name = _name, \
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.base_pa = _base_pa, \
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.base_va = _base_va, \
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.size = _size, \
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.attrs = _attrs, \
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}
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#define MMU_REGION_FLAT_ENTRY(name, adr, sz, attrs) \
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MMU_REGION_ENTRY(name, adr, adr, sz, attrs)
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/* Region definition data structure */
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struct arm_mmu_region {
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/* Region Base Physical Address */
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uintptr_t base_pa;
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/* Region Base Virtual Address */
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uintptr_t base_va;
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/* Region size */
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size_t size;
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/* Region Name */
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const char *name;
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/* Region Attributes */
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uint32_t attrs;
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};
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/* MMU configuration data structure */
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struct arm_mmu_config {
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/* Number of regions */
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uint32_t num_regions;
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/* Regions */
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const struct arm_mmu_region *mmu_regions;
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};
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/*
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* Reference to the MMU configuration.
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*
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* This struct is defined and populated for each SoC (in the SoC definition),
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* and holds the build-time configuration information for the fixed MMU
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* regions enabled during kernel initialization.
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*/
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extern const struct arm_mmu_config mmu_config;
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int z_arm_mmu_init(void);
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_INCLUDE_ARCH_AARCH32_ARM_MMU_H_ */
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