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soc: arm: nxp_s32: s32k1: fix code cache init

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Currently Code Cache cannot be enabled because its initialization is
guarded by Kconfig options which depend on CPU core cache support,
but S32K14x devices has a SoC specific L1 cache controller. Hence,
introduce a SoC-specific symbol to enable Code Cache.

Note that the cache controller is not available for S32K11x devices.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit is contained in:
Manuel Argüelles 2023-12-05 19:29:42 +07:00 • committed by Fabio Baltieri
commit 6aa242cdfb
2 changed files with 12 additions and 1 deletions
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11
soc/arm/nxp_s32/s32k1/Kconfig.soc
View file

@ -20,36 +20,42 @@ config SOC_S32K142
select CPU_CORTEX_M4 select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU select CPU_HAS_FPU
select HAS_MCUX_CACHE
config SOC_S32K142W config SOC_S32K142W
bool "S32K142W" bool "S32K142W"
select CPU_CORTEX_M4 select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU select CPU_HAS_FPU
select HAS_MCUX_CACHE
config SOC_S32K144 config SOC_S32K144
bool "S32K144" bool "S32K144"
select CPU_CORTEX_M4 select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU select CPU_HAS_FPU
select HAS_MCUX_CACHE
config SOC_S32K144W config SOC_S32K144W
bool "S32K144W" bool "S32K144W"
select CPU_CORTEX_M4 select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU select CPU_HAS_FPU
select HAS_MCUX_CACHE
config SOC_S32K146 config SOC_S32K146
bool "S32K146" bool "S32K146"
select CPU_CORTEX_M4 select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU select CPU_HAS_FPU
select HAS_MCUX_CACHE
config SOC_S32K148 config SOC_S32K148
bool "S32K148" bool "S32K148"
select CPU_CORTEX_M4 select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU select CPU_HAS_FPU
select HAS_MCUX_CACHE
endchoice endchoice
@ -431,4 +437,9 @@ config NXP_S32_FLASH_CONFIG_FDPROT
endif # NXP_S32_FLASH_CONFIG endif # NXP_S32_FLASH_CONFIG
config NXP_S32_ENABLE_CODE_CACHE
bool "Code cache"
default y
depends on HAS_MCUX_CACHE
endif # SOC_SERIES_S32K1XX endif # SOC_SERIES_S32K1XX

2
soc/arm/nxp_s32/s32k1/soc.c
View file

@ -63,7 +63,7 @@ static int soc_init(void)
IP_MPU->CESR = tmp; IP_MPU->CESR = tmp;
#endif /* !CONFIG_ARM_MPU */ #endif /* !CONFIG_ARM_MPU */
#if defined(CONFIG_DCACHE) && defined(CONFIG_ICACHE) #if defined(CONFIG_HAS_MCUX_CACHE) && defined(CONFIG_NXP_S32_ENABLE_CODE_CACHE)
/* Invalidate all ways */ /* Invalidate all ways */
IP_LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK; IP_LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK;
IP_LMEM->PCCCR |= LMEM_PCCCR_GO_MASK; IP_LMEM->PCCCR |= LMEM_PCCCR_GO_MASK;