From 6aa242cdfb8165104858aa8d857e2a8bc3ff4b70 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Manuel=20Arg=C3=BCelles?= Date: Tue, 5 Dec 2023 19:29:42 +0700 Subject: [PATCH] soc: arm: nxp_s32: s32k1: fix code cache init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently Code Cache cannot be enabled because its initialization is guarded by Kconfig options which depend on CPU core cache support, but S32K14x devices has a SoC specific L1 cache controller. Hence, introduce a SoC-specific symbol to enable Code Cache. Note that the cache controller is not available for S32K11x devices. Signed-off-by: Manuel Argüelles --- soc/arm/nxp_s32/s32k1/Kconfig.soc | 11 +++++++++++ soc/arm/nxp_s32/s32k1/soc.c | 2 +- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/soc/arm/nxp_s32/s32k1/Kconfig.soc b/soc/arm/nxp_s32/s32k1/Kconfig.soc index dd1cdf77538..78caf49f677 100644 --- a/soc/arm/nxp_s32/s32k1/Kconfig.soc +++ b/soc/arm/nxp_s32/s32k1/Kconfig.soc @@ -20,36 +20,42 @@ config SOC_S32K142 select CPU_CORTEX_M4 select CPU_CORTEX_M_HAS_DWT select CPU_HAS_FPU + select HAS_MCUX_CACHE config SOC_S32K142W bool "S32K142W" select CPU_CORTEX_M4 select CPU_CORTEX_M_HAS_DWT select CPU_HAS_FPU + select HAS_MCUX_CACHE config SOC_S32K144 bool "S32K144" select CPU_CORTEX_M4 select CPU_CORTEX_M_HAS_DWT select CPU_HAS_FPU + select HAS_MCUX_CACHE config SOC_S32K144W bool "S32K144W" select CPU_CORTEX_M4 select CPU_CORTEX_M_HAS_DWT select CPU_HAS_FPU + select HAS_MCUX_CACHE config SOC_S32K146 bool "S32K146" select CPU_CORTEX_M4 select CPU_CORTEX_M_HAS_DWT select CPU_HAS_FPU + select HAS_MCUX_CACHE config SOC_S32K148 bool "S32K148" select CPU_CORTEX_M4 select CPU_CORTEX_M_HAS_DWT select CPU_HAS_FPU + select HAS_MCUX_CACHE endchoice @@ -431,4 +437,9 @@ config NXP_S32_FLASH_CONFIG_FDPROT endif # NXP_S32_FLASH_CONFIG +config NXP_S32_ENABLE_CODE_CACHE + bool "Code cache" + default y + depends on HAS_MCUX_CACHE + endif # SOC_SERIES_S32K1XX diff --git a/soc/arm/nxp_s32/s32k1/soc.c b/soc/arm/nxp_s32/s32k1/soc.c index 8c73b4fa6f5..175b6fe6442 100644 --- a/soc/arm/nxp_s32/s32k1/soc.c +++ b/soc/arm/nxp_s32/s32k1/soc.c @@ -63,7 +63,7 @@ static int soc_init(void) IP_MPU->CESR = tmp; #endif /* !CONFIG_ARM_MPU */ -#if defined(CONFIG_DCACHE) && defined(CONFIG_ICACHE) +#if defined(CONFIG_HAS_MCUX_CACHE) && defined(CONFIG_NXP_S32_ENABLE_CODE_CACHE) /* Invalidate all ways */ IP_LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK; IP_LMEM->PCCCR |= LMEM_PCCCR_GO_MASK;