arch/riscv: Adding KConfig options for 'A' and 'M' RISC-V extensions
New KConfig options for 'A' and 'M' RISC-V extensions have been added. These are used to configure the '-march' string used by GCC to produce a compatible binary for the requested RISC-V variant. In order to maintain compatibility with all currently defined SoC, default the options for HW mul / Atomics support to 'y', but allow them to be overridden for any SoC which does not support these. I tested this change locally via twister agaisnt a few RISC-V platforms including some 32bit and 64bit. To verify the 4 possibilities of Atomics & HW Mul: (No, No), (No, Yes), (Yes, No), (Yes, Yes -- current behavior), I used an out-of-tree GCC (xPack RISC-V GCC) which has multilib support for rv32i, rv32ia, rv32ima to test against our out-of-tree Intel Nios V/m processor in HW. The Zephyr SDK RISCV GCC currently does not contain multilib support for all variants exposed by these new KConfig options. Signed-off-by: Nathan Krueger <nathan.krueger@intel.com>
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2 changed files with 17 additions and 2 deletions
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@ -13,6 +13,14 @@ config COMPRESSED_ISA
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bool
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default y if 64BIT
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config RISCV_ATOMICS_ISA
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bool "RISC-V atomics 'a' extension"
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default y
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config RISCV_MUL_ISA
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bool "RISC-V HW multiply 'm' extension"
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default y
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config FLOAT_HARD
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bool "Hard-float calling convention"
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default y
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@ -5,12 +5,19 @@ set(riscv_march "rv")
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if(CONFIG_64BIT)
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string(CONCAT riscv_mabi ${riscv_mabi} "64")
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string(CONCAT riscv_march ${riscv_march} "64ima")
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string(CONCAT riscv_march ${riscv_march} "64i")
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list(APPEND TOOLCHAIN_C_FLAGS -mcmodel=medany)
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list(APPEND TOOLCHAIN_LD_FLAGS -mcmodel=medany)
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else()
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string(CONCAT riscv_mabi "i" ${riscv_mabi} "32")
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string(CONCAT riscv_march ${riscv_march} "32ima")
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string(CONCAT riscv_march ${riscv_march} "32i")
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endif()
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if (CONFIG_RISCV_MUL_ISA)
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string(CONCAT riscv_march ${riscv_march} "m")
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endif()
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if (CONFIG_RISCV_ATOMICS_ISA)
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string(CONCAT riscv_march ${riscv_march} "a")
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endif()
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if(CONFIG_FPU)
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