arch: arm: nrf: Use SystemInit() from MDK in SoC initialization
Replace code that handles erratas and performs other SoC-specific initialization, that was actually copied from SystemInit() provided in MDK for particular SoCs, with a call to SystemInit(). Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit is contained in:
Andrzej Głąbek
Carles Cufí
parent
0a6046cf31
commit
687355c9af
3 changed files with 15 additions and 463 deletions
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@ -25,14 +25,7 @@ extern void _NmiInit(void);
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#define NMI_INIT()
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#endif
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#include "nrf.h"
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#define __SYSTEM_CLOCK (16000000UL)
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static bool ftpan_26(void);
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static bool ftpan_59(void);
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uint32_t SystemCoreClock __used = __SYSTEM_CLOCK;
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#include <system_nrf51.h>
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static int nordicsemi_nrf51_init(struct device *arg)
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{
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@ -40,37 +33,9 @@ static int nordicsemi_nrf51_init(struct device *arg)
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ARG_UNUSED(arg);
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/* Note:
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* Magic numbers below are obtained by reading the registers
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* when the SoC was running the SAM-BA bootloader
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* (with reserved bits set to 0).
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*/
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key = irq_lock();
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/* Prepare the peripherals for use as indicated by the PAN 26 "System:
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* Manual setup is required to enable the use of peripherals" found at
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* Product Anomaly document for your device found at
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* https://www.nordicsemi.com/. The side effect of executing these
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* instructions in the devices that do not need it is that the new
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* peripherals in the second generation devices (LPCOMP for example)
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* will not be available.
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*/
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if (ftpan_26()) {
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*(volatile u32_t *)0x40000504 = 0xC007FFDF;
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*(volatile u32_t *)0x40006C18 = 0x00008000;
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}
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/* Disable PROTENSET registers under debug, as indicated by PAN 59
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* "MPU: Reset value of DISABLEINDEBUG register is incorrect" found
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* at Product Anomaly document for your device found at
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* https://www.nordicsemi.com/.
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*/
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if (ftpan_59()) {
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NRF_MPU->DISABLEINDEBUG =
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MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled <<
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MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos;
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}
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SystemInit();
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/* Install default handler that simply resets the CPU
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* if configured in the kernel, NOP otherwise
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@ -82,38 +47,4 @@ static int nordicsemi_nrf51_init(struct device *arg)
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return 0;
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}
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static bool ftpan_26(void)
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{
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if ((((*(u32_t *)0xF0000FE0) & 0x000000FF) == 0x1) &&
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(((*(u32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
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if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x00) &&
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(((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
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return true;
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}
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if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x10) &&
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(((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
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return true;
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}
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if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
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(((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
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return true;
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}
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}
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return false;
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}
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static bool ftpan_59(void)
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{
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if ((((*(u32_t *)0xF0000FE0) & 0x000000FF) == 0x1) &&
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(((*(u32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
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if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x40) &&
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(((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
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return true;
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}
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}
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return false;
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}
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SYS_INIT(nordicsemi_nrf51_init, PRE_KERNEL_1, 0);
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@ -25,354 +25,16 @@ extern void _NmiInit(void);
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#define NMI_INIT()
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#endif
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#include "nrf.h"
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#include "nrf_power.h"
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#define __SYSTEM_CLOCK_64M (64000000UL)
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#ifdef CONFIG_SOC_NRF52832
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static bool ftpan_32(void)
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{
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if ((((*(u32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
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(((*(u32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
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if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
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(((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
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return true;
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}
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}
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return false;
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}
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static bool ftpan_37(void)
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{
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if ((((*(u32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
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(((*(u32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
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if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
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(((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
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return true;
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}
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}
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return false;
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}
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static bool ftpan_36(void)
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{
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if ((((*(u32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
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(((*(u32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
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if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
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(((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
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return true;
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}
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}
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return false;
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}
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static bool errata_136_nrf52832(void)
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{
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if ((((*(u32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
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(((*(u32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
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if (((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x30) {
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return true;
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}
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if (((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x40) {
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return true;
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}
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if (((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x50) {
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return true;
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}
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}
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return false;
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}
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static void nordicsemi_nrf52832_init(void)
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{
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/* Workaround for FTPAN-32 "DIF: Debug session automatically
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* enables TracePort pins" found at Product Anomaly document
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* for your device located at https://www.nordicsemi.com/
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*/
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if (ftpan_32()) {
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CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk;
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}
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/* Workaround for FTPAN-37 "AMLI: EasyDMA is slow with Radio,
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* ECB, AAR and CCM." found at Product Anomaly document
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* for your device located at https://www.nordicsemi.com/
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*/
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if (ftpan_37()) {
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*(volatile u32_t *)0x400005A0 = 0x3;
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}
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/* Workaround for FTPAN-36 "CLOCK: Some registers are not
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* reset when expected." found at Product Anomaly document
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* for your device located at https://www.nordicsemi.com/
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*/
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if (ftpan_36()) {
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NRF_CLOCK->EVENTS_DONE = 0;
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NRF_CLOCK->EVENTS_CTTO = 0;
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}
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/* Workaround for Errata 136 "System: Bits in RESETREAS are set when
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* they should not be" found at the Errata document for your device
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* located at https://infocenter.nordicsemi.com/
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*/
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if (errata_136_nrf52832()) {
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if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk) {
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NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk;
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}
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}
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/* Configure GPIO pads as pPin Reset pin if Pin Reset
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* capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
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* defined, pin reset will not be available. One GPIO (see
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* Product Specification to see which one) will then be
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* reserved for PinReset and not available as normal GPIO.
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*/
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#if defined(CONFIG_GPIO_AS_PINRESET)
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if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) !=
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(UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
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((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) !=
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(UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))) {
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NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
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while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
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;
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}
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NRF_UICR->PSELRESET[0] = 21;
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while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
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;
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}
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NRF_UICR->PSELRESET[1] = 21;
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while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
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;
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}
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NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
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while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
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;
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}
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NVIC_SystemReset();
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}
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#if defined(CONFIG_SOC_NRF52832)
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#include <system_nrf52.h>
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#elif defined(CONFIG_SOC_NRF52840)
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#include <system_nrf52840.h>
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#else
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#error "Unknown SoC."
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#endif
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/* Enable SWO trace functionality. If ENABLE_SWO is not
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* defined, SWO pin will be used as GPIO (see Product
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* Specification to see which one).
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*/
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#if defined(ENABLE_SWO)
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CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
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NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial <<
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CLOCK_TRACECONFIG_TRACEMUX_Pos;
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#endif
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/* Enable Trace functionality. If ENABLE_TRACE is not
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* defined, TRACE pins will be used as GPIOs (see Product
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* Specification to see which ones).
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*/
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#if defined(ENABLE_TRACE)
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CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
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NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel <<
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CLOCK_TRACECONFIG_TRACEMUX_Pos;
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#endif
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}
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#endif /* CONFIG_SOC_NRF52832 */
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#ifdef CONFIG_SOC_NRF52840
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static bool errata_36(void)
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{
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if ((*(u32_t *)0x10000130ul == 0x8ul) &&
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(*(u32_t *)0x10000134ul == 0x0ul)) {
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return true;
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}
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return false;
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}
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static bool errata_98(void)
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{
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if ((*(u32_t *)0x10000130ul == 0x8ul) &&
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(*(u32_t *)0x10000134ul == 0x0ul)) {
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return true;
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}
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return false;
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}
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static bool errata_103(void)
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{
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if ((*(u32_t *)0x10000130ul == 0x8ul) &&
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(*(u32_t *)0x10000134ul == 0x0ul)) {
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return true;
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}
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return false;
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}
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static bool errata_115(void)
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{
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if ((*(u32_t *)0x10000130ul == 0x8ul) &&
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(*(u32_t *)0x10000134ul == 0x0ul)) {
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return true;
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}
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return false;
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}
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static bool errata_120(void)
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{
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if ((*(u32_t *)0x10000130ul == 0x8ul) &&
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(*(u32_t *)0x10000134ul == 0x0ul)) {
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return true;
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}
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return false;
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}
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static bool errata_136_nrf52840(void)
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{
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if ((*(u32_t *)0x10000130ul == 0x8ul) &&
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(*(u32_t *)0x10000134ul == 0x0ul)) {
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return true;
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}
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return false;
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}
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static void nordicsemi_nrf52840_init(void)
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{
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/* Workaround for Errata 36 "CLOCK: Some registers are not reset when
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* expected" found at the Errata document for your device located at
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* https://infocenter.nordicsemi.com/
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*/
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if (errata_36()) {
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NRF_CLOCK->EVENTS_DONE = 0;
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NRF_CLOCK->EVENTS_CTTO = 0;
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NRF_CLOCK->CTIV = 0;
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}
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/* Workaround for Errata 98 "NFCT: Not able to communicate with the
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* peer" found at the Errata document for your device located at
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* https://infocenter.nordicsemi.com/
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*/
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if (errata_98()) {
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*(volatile u32_t *)0x4000568Cul = 0x00038148ul;
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}
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/* Workaround for Errata 103 "CCM: Wrong reset value of CCM
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* MAXPACKETSIZE" found at the Errata document for your device
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* located at https://infocenter.nordicsemi.com/
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*/
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if (errata_103()) {
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NRF_CCM->MAXPACKETSIZE = 0xFBul;
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}
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/* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon
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* waking up from System ON Idle or System OFF mode" found at the
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* Errata document for your device located at
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* https://infocenter.nordicsemi.com/
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*/
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if (errata_115()) {
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*(volatile u32_t *)0x40000EE4 =
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(*(volatile u32_t *) 0x40000EE4 & 0xFFFFFFF0) |
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(*(u32_t *)0x10000258 & 0x0000000F);
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}
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/* Workaround for Errata 120 "QSPI: Data read or written is corrupted"
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* found at the Errata document for your device located at
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* https://infocenter.nordicsemi.com/
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*/
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if (errata_120()) {
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*(volatile u32_t *)0x40029640ul = 0x200ul;
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}
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/* Workaround for Errata 136 "System: Bits in RESETREAS are set when
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* they should not be" found at the Errata document for your device
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* located at https://infocenter.nordicsemi.com/
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*/
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if (errata_136_nrf52840()) {
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if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk) {
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NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk;
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}
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}
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/* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities
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* desired.
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* If CONFIG_GPIO_AS_PINRESET is not defined, pin reset will not be
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* available. One GPIO (see Product Specification to see which one) will
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* then be reserved for PinReset and not available as normal GPIO.
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*/
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#if defined(CONFIG_GPIO_AS_PINRESET)
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if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) !=
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(UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
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((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) !=
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(UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))) {
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NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
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while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
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}
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NRF_UICR->PSELRESET[0] = 18;
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while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
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}
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NRF_UICR->PSELRESET[1] = 18;
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while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
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}
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NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
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while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
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}
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NVIC_SystemReset();
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}
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#endif
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/* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin
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* will be used as GPIO (see Product Specification to see which one).
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*/
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#if defined(ENABLE_SWO)
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CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
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NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial <<
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CLOCK_TRACECONFIG_TRACEMUX_Pos;
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NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos)
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| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) |
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(GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
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#endif
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/* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE
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* pins will be used as GPIOs (see Product Specification to see which
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* ones).
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*/
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#if defined(ENABLE_TRACE)
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CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
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NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel <<
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CLOCK_TRACECONFIG_TRACEMUX_Pos;
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NRF_P0->PIN_CNF[7] = (GPIO_PIN_CNF_DRIVE_H0H1 <<
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GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect <<
|
||||
GPIO_PIN_CNF_INPUT_Pos) |
|
||||
(GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 <<
|
||||
GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect <<
|
||||
GPIO_PIN_CNF_INPUT_Pos) |
|
||||
(GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
NRF_P0->PIN_CNF[12] = (GPIO_PIN_CNF_DRIVE_H0H1 <<
|
||||
GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect <<
|
||||
GPIO_PIN_CNF_INPUT_Pos) |
|
||||
(GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
NRF_P0->PIN_CNF[11] = (GPIO_PIN_CNF_DRIVE_H0H1 <<
|
||||
GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect <<
|
||||
GPIO_PIN_CNF_INPUT_Pos) |
|
||||
(GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
NRF_P1->PIN_CNF[9] = (GPIO_PIN_CNF_DRIVE_H0H1 <<
|
||||
GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect <<
|
||||
GPIO_PIN_CNF_INPUT_Pos) |
|
||||
(GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
#endif
|
||||
}
|
||||
#endif /* CONFIG_SOC_NRF52840 */
|
||||
|
||||
uint32_t SystemCoreClock __used = __SYSTEM_CLOCK_64M;
|
||||
|
||||
static void clock_init(void)
|
||||
{
|
||||
SystemCoreClock = __SYSTEM_CLOCK_64M;
|
||||
}
|
||||
#include <nrf.h>
|
||||
#include <hal/nrf_power.h>
|
||||
|
||||
static int nordicsemi_nrf52_init(struct device *arg)
|
||||
{
|
||||
|
|
@ -382,53 +44,11 @@ static int nordicsemi_nrf52_init(struct device *arg)
|
|||
|
||||
key = irq_lock();
|
||||
|
||||
#ifdef CONFIG_SOC_NRF52832
|
||||
nordicsemi_nrf52832_init();
|
||||
#endif
|
||||
#ifdef CONFIG_SOC_NRF52840
|
||||
nordicsemi_nrf52840_init();
|
||||
#endif
|
||||
SystemInit();
|
||||
|
||||
#ifdef CONFIG_NRF_ENABLE_ICACHE
|
||||
/* Enable the instruction cache */
|
||||
NRF_NVMC->ICACHECNF = NVMC_ICACHECNF_CACHEEN_Msk;
|
||||
#endif /* CONFIG_NRF_ENABLE_ICACHE */
|
||||
|
||||
/* Enable the FPU if the compiler used floating point unit
|
||||
* instructions. Since the FPU consumes energy, remember to
|
||||
* disable FPU use in the compiler if floating point unit
|
||||
* operations are not used in your code.
|
||||
*/
|
||||
#if defined(CONFIG_FLOAT)
|
||||
SCB->CPACR |= (3UL << 20) | (3UL << 22);
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
|
||||
/* Configure NFCT pins as GPIOs if NFCT is not to be used in
|
||||
* your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
|
||||
* two GPIOs (see Product Specification to see which ones)
|
||||
* will be reserved for NFC and will not be available as
|
||||
* normal GPIOs.
|
||||
*/
|
||||
#if defined(CONFIG_NFCT_PINS_AS_GPIOS)
|
||||
if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) ==
|
||||
(UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)) {
|
||||
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
|
||||
;
|
||||
}
|
||||
NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
|
||||
;
|
||||
}
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
|
||||
;
|
||||
}
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SOC_DCDC_NRF52X)
|
||||
|
|
@ -437,9 +57,6 @@ static int nordicsemi_nrf52_init(struct device *arg)
|
|||
|
||||
_ClearFaults();
|
||||
|
||||
/* Setup master clock */
|
||||
clock_init();
|
||||
|
||||
/* Install default handler that simply resets the CPU
|
||||
* if configured in the kernel, NOP otherwise
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -4,6 +4,10 @@ if(CONFIG_HAS_NORDIC_DRIVERS)
|
|||
add_subdirectory(drivers)
|
||||
endif()
|
||||
|
||||
zephyr_sources_ifdef(CONFIG_SOC_SERIES_NRF51X nrfx/mdk/system_nrf51.c)
|
||||
zephyr_sources_ifdef(CONFIG_SOC_NRF52832 nrfx/mdk/system_nrf52.c)
|
||||
zephyr_sources_ifdef(CONFIG_SOC_NRF52840 nrfx/mdk/system_nrf52840.c)
|
||||
|
||||
if(CONFIG_HAS_NRFX)
|
||||
zephyr_include_directories(nrfx)
|
||||
zephyr_include_directories(nrfx/drivers/include)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue