From 687355c9af5ab8bd5f739e22eba26d94f75d615c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20G=C5=82=C4=85bek?= Date: Mon, 18 Jun 2018 10:35:43 +0200 Subject: [PATCH] arch: arm: nrf: Use SystemInit() from MDK in SoC initialization MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace code that handles erratas and performs other SoC-specific initialization, that was actually copied from SystemInit() provided in MDK for particular SoCs, with a call to SystemInit(). Signed-off-by: Andrzej Głąbek --- arch/arm/soc/nordic_nrf/nrf51/soc.c | 73 +---- arch/arm/soc/nordic_nrf/nrf52/soc.c | 401 +--------------------------- ext/hal/nordic/CMakeLists.txt | 4 + 3 files changed, 15 insertions(+), 463 deletions(-) diff --git a/arch/arm/soc/nordic_nrf/nrf51/soc.c b/arch/arm/soc/nordic_nrf/nrf51/soc.c index db9bacb75f3..3188ac29f89 100644 --- a/arch/arm/soc/nordic_nrf/nrf51/soc.c +++ b/arch/arm/soc/nordic_nrf/nrf51/soc.c @@ -25,14 +25,7 @@ extern void _NmiInit(void); #define NMI_INIT() #endif -#include "nrf.h" - -#define __SYSTEM_CLOCK (16000000UL) - -static bool ftpan_26(void); -static bool ftpan_59(void); - -uint32_t SystemCoreClock __used = __SYSTEM_CLOCK; +#include static int nordicsemi_nrf51_init(struct device *arg) { @@ -40,37 +33,9 @@ static int nordicsemi_nrf51_init(struct device *arg) ARG_UNUSED(arg); - /* Note: - * Magic numbers below are obtained by reading the registers - * when the SoC was running the SAM-BA bootloader - * (with reserved bits set to 0). - */ - key = irq_lock(); - /* Prepare the peripherals for use as indicated by the PAN 26 "System: - * Manual setup is required to enable the use of peripherals" found at - * Product Anomaly document for your device found at - * https://www.nordicsemi.com/. The side effect of executing these - * instructions in the devices that do not need it is that the new - * peripherals in the second generation devices (LPCOMP for example) - * will not be available. - */ - if (ftpan_26()) { - *(volatile u32_t *)0x40000504 = 0xC007FFDF; - *(volatile u32_t *)0x40006C18 = 0x00008000; - } - - /* Disable PROTENSET registers under debug, as indicated by PAN 59 - * "MPU: Reset value of DISABLEINDEBUG register is incorrect" found - * at Product Anomaly document for your device found at - * https://www.nordicsemi.com/. - */ - if (ftpan_59()) { - NRF_MPU->DISABLEINDEBUG = - MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled << - MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos; - } + SystemInit(); /* Install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise @@ -82,38 +47,4 @@ static int nordicsemi_nrf51_init(struct device *arg) return 0; } -static bool ftpan_26(void) -{ - if ((((*(u32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && - (((*(u32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) { - if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x00) && - (((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) { - return true; - } - if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x10) && - (((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) { - return true; - } - if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x30) && - (((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) { - return true; - } - } - - return false; -} - -static bool ftpan_59(void) -{ - if ((((*(u32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && - (((*(u32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) { - if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x40) && - (((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) { - return true; - } - } - - return false; -} - SYS_INIT(nordicsemi_nrf51_init, PRE_KERNEL_1, 0); diff --git a/arch/arm/soc/nordic_nrf/nrf52/soc.c b/arch/arm/soc/nordic_nrf/nrf52/soc.c index 5290fd3e87f..36f2b13d578 100644 --- a/arch/arm/soc/nordic_nrf/nrf52/soc.c +++ b/arch/arm/soc/nordic_nrf/nrf52/soc.c @@ -25,354 +25,16 @@ extern void _NmiInit(void); #define NMI_INIT() #endif -#include "nrf.h" -#include "nrf_power.h" - -#define __SYSTEM_CLOCK_64M (64000000UL) - -#ifdef CONFIG_SOC_NRF52832 -static bool ftpan_32(void) -{ - if ((((*(u32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && - (((*(u32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) { - if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x30) && - (((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) { - return true; - } - } - - return false; -} - -static bool ftpan_37(void) -{ - if ((((*(u32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && - (((*(u32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) { - if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x30) && - (((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) { - return true; - } - } - - return false; -} - -static bool ftpan_36(void) -{ - if ((((*(u32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && - (((*(u32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) { - if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x30) && - (((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) { - return true; - } - } - - return false; -} - -static bool errata_136_nrf52832(void) -{ - if ((((*(u32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && - (((*(u32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) { - if (((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x30) { - return true; - } - if (((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x40) { - return true; - } - if (((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x50) { - return true; - } - } - - return false; -} - -static void nordicsemi_nrf52832_init(void) -{ - /* Workaround for FTPAN-32 "DIF: Debug session automatically - * enables TracePort pins" found at Product Anomaly document - * for your device located at https://www.nordicsemi.com/ - */ - if (ftpan_32()) { - CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; - } - - /* Workaround for FTPAN-37 "AMLI: EasyDMA is slow with Radio, - * ECB, AAR and CCM." found at Product Anomaly document - * for your device located at https://www.nordicsemi.com/ - */ - if (ftpan_37()) { - *(volatile u32_t *)0x400005A0 = 0x3; - } - - /* Workaround for FTPAN-36 "CLOCK: Some registers are not - * reset when expected." found at Product Anomaly document - * for your device located at https://www.nordicsemi.com/ - */ - if (ftpan_36()) { - NRF_CLOCK->EVENTS_DONE = 0; - NRF_CLOCK->EVENTS_CTTO = 0; - } - - /* Workaround for Errata 136 "System: Bits in RESETREAS are set when - * they should not be" found at the Errata document for your device - * located at https://infocenter.nordicsemi.com/ - */ - if (errata_136_nrf52832()) { - if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk) { - NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk; - } - } - - /* Configure GPIO pads as pPin Reset pin if Pin Reset - * capabilities desired. If CONFIG_GPIO_AS_PINRESET is not - * defined, pin reset will not be available. One GPIO (see - * Product Specification to see which one) will then be - * reserved for PinReset and not available as normal GPIO. - */ -#if defined(CONFIG_GPIO_AS_PINRESET) - if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != - (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) || - ((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != - (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))) { - - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { - ; - } - NRF_UICR->PSELRESET[0] = 21; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { - ; - } - NRF_UICR->PSELRESET[1] = 21; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { - ; - } - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { - ; - } - NVIC_SystemReset(); - } +#if defined(CONFIG_SOC_NRF52832) +#include +#elif defined(CONFIG_SOC_NRF52840) +#include +#else +#error "Unknown SoC." #endif - /* Enable SWO trace functionality. If ENABLE_SWO is not - * defined, SWO pin will be used as GPIO (see Product - * Specification to see which one). - */ -#if defined(ENABLE_SWO) - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << - CLOCK_TRACECONFIG_TRACEMUX_Pos; -#endif - - /* Enable Trace functionality. If ENABLE_TRACE is not - * defined, TRACE pins will be used as GPIOs (see Product - * Specification to see which ones). - */ -#if defined(ENABLE_TRACE) - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << - CLOCK_TRACECONFIG_TRACEMUX_Pos; -#endif -} -#endif /* CONFIG_SOC_NRF52832 */ - -#ifdef CONFIG_SOC_NRF52840 -static bool errata_36(void) -{ - if ((*(u32_t *)0x10000130ul == 0x8ul) && - (*(u32_t *)0x10000134ul == 0x0ul)) { - return true; - } - - return false; -} - -static bool errata_98(void) -{ - if ((*(u32_t *)0x10000130ul == 0x8ul) && - (*(u32_t *)0x10000134ul == 0x0ul)) { - return true; - } - - return false; -} - -static bool errata_103(void) -{ - if ((*(u32_t *)0x10000130ul == 0x8ul) && - (*(u32_t *)0x10000134ul == 0x0ul)) { - return true; - } - - return false; -} - -static bool errata_115(void) -{ - if ((*(u32_t *)0x10000130ul == 0x8ul) && - (*(u32_t *)0x10000134ul == 0x0ul)) { - return true; - } - - return false; -} - -static bool errata_120(void) -{ - if ((*(u32_t *)0x10000130ul == 0x8ul) && - (*(u32_t *)0x10000134ul == 0x0ul)) { - return true; - } - - return false; -} - -static bool errata_136_nrf52840(void) -{ - if ((*(u32_t *)0x10000130ul == 0x8ul) && - (*(u32_t *)0x10000134ul == 0x0ul)) { - return true; - } - - return false; -} - -static void nordicsemi_nrf52840_init(void) -{ - /* Workaround for Errata 36 "CLOCK: Some registers are not reset when - * expected" found at the Errata document for your device located at - * https://infocenter.nordicsemi.com/ - */ - if (errata_36()) { - NRF_CLOCK->EVENTS_DONE = 0; - NRF_CLOCK->EVENTS_CTTO = 0; - NRF_CLOCK->CTIV = 0; - } - - /* Workaround for Errata 98 "NFCT: Not able to communicate with the - * peer" found at the Errata document for your device located at - * https://infocenter.nordicsemi.com/ - */ - if (errata_98()) { - *(volatile u32_t *)0x4000568Cul = 0x00038148ul; - } - - /* Workaround for Errata 103 "CCM: Wrong reset value of CCM - * MAXPACKETSIZE" found at the Errata document for your device - * located at https://infocenter.nordicsemi.com/ - */ - if (errata_103()) { - NRF_CCM->MAXPACKETSIZE = 0xFBul; - } - - /* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon - * waking up from System ON Idle or System OFF mode" found at the - * Errata document for your device located at - * https://infocenter.nordicsemi.com/ - */ - if (errata_115()) { - *(volatile u32_t *)0x40000EE4 = - (*(volatile u32_t *) 0x40000EE4 & 0xFFFFFFF0) | - (*(u32_t *)0x10000258 & 0x0000000F); - } - - /* Workaround for Errata 120 "QSPI: Data read or written is corrupted" - * found at the Errata document for your device located at - * https://infocenter.nordicsemi.com/ - */ - if (errata_120()) { - *(volatile u32_t *)0x40029640ul = 0x200ul; - } - - /* Workaround for Errata 136 "System: Bits in RESETREAS are set when - * they should not be" found at the Errata document for your device - * located at https://infocenter.nordicsemi.com/ - */ - if (errata_136_nrf52840()) { - if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk) { - NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk; - } - } - - /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities - * desired. - * If CONFIG_GPIO_AS_PINRESET is not defined, pin reset will not be - * available. One GPIO (see Product Specification to see which one) will - * then be reserved for PinReset and not available as normal GPIO. - */ -#if defined(CONFIG_GPIO_AS_PINRESET) - if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != - (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) || - ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != - (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))) { - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { - } - NRF_UICR->PSELRESET[0] = 18; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { - } - NRF_UICR->PSELRESET[1] = 18; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { - } - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { - } - NVIC_SystemReset(); - } -#endif - /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin - * will be used as GPIO (see Product Specification to see which one). - */ -#if defined(ENABLE_SWO) - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << - CLOCK_TRACECONFIG_TRACEMUX_Pos; - NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) - | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | - (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); -#endif - - /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE - * pins will be used as GPIOs (see Product Specification to see which - * ones). - */ -#if defined(ENABLE_TRACE) - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << - CLOCK_TRACECONFIG_TRACEMUX_Pos; - NRF_P0->PIN_CNF[7] = (GPIO_PIN_CNF_DRIVE_H0H1 << - GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << - GPIO_PIN_CNF_INPUT_Pos) | - (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << - GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << - GPIO_PIN_CNF_INPUT_Pos) | - (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - NRF_P0->PIN_CNF[12] = (GPIO_PIN_CNF_DRIVE_H0H1 << - GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << - GPIO_PIN_CNF_INPUT_Pos) | - (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - NRF_P0->PIN_CNF[11] = (GPIO_PIN_CNF_DRIVE_H0H1 << - GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << - GPIO_PIN_CNF_INPUT_Pos) | - (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - NRF_P1->PIN_CNF[9] = (GPIO_PIN_CNF_DRIVE_H0H1 << - GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << - GPIO_PIN_CNF_INPUT_Pos) | - (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); -#endif -} -#endif /* CONFIG_SOC_NRF52840 */ - -uint32_t SystemCoreClock __used = __SYSTEM_CLOCK_64M; - -static void clock_init(void) -{ - SystemCoreClock = __SYSTEM_CLOCK_64M; -} +#include +#include static int nordicsemi_nrf52_init(struct device *arg) { @@ -382,53 +44,11 @@ static int nordicsemi_nrf52_init(struct device *arg) key = irq_lock(); -#ifdef CONFIG_SOC_NRF52832 - nordicsemi_nrf52832_init(); -#endif -#ifdef CONFIG_SOC_NRF52840 - nordicsemi_nrf52840_init(); -#endif + SystemInit(); #ifdef CONFIG_NRF_ENABLE_ICACHE /* Enable the instruction cache */ NRF_NVMC->ICACHECNF = NVMC_ICACHECNF_CACHEEN_Msk; -#endif /* CONFIG_NRF_ENABLE_ICACHE */ - - /* Enable the FPU if the compiler used floating point unit - * instructions. Since the FPU consumes energy, remember to - * disable FPU use in the compiler if floating point unit - * operations are not used in your code. - */ -#if defined(CONFIG_FLOAT) - SCB->CPACR |= (3UL << 20) | (3UL << 22); - __DSB(); - __ISB(); -#endif - - /* Configure NFCT pins as GPIOs if NFCT is not to be used in - * your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined, - * two GPIOs (see Product Specification to see which ones) - * will be reserved for NFC and will not be available as - * normal GPIOs. - */ -#if defined(CONFIG_NFCT_PINS_AS_GPIOS) - if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == - (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)) { - - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { - ; - } - NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { - ; - } - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { - ; - } - NVIC_SystemReset(); - } #endif #if defined(CONFIG_SOC_DCDC_NRF52X) @@ -437,9 +57,6 @@ static int nordicsemi_nrf52_init(struct device *arg) _ClearFaults(); - /* Setup master clock */ - clock_init(); - /* Install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise */ diff --git a/ext/hal/nordic/CMakeLists.txt b/ext/hal/nordic/CMakeLists.txt index 23504b0dfa6..7bfe7553622 100644 --- a/ext/hal/nordic/CMakeLists.txt +++ b/ext/hal/nordic/CMakeLists.txt @@ -4,6 +4,10 @@ if(CONFIG_HAS_NORDIC_DRIVERS) add_subdirectory(drivers) endif() +zephyr_sources_ifdef(CONFIG_SOC_SERIES_NRF51X nrfx/mdk/system_nrf51.c) +zephyr_sources_ifdef(CONFIG_SOC_NRF52832 nrfx/mdk/system_nrf52.c) +zephyr_sources_ifdef(CONFIG_SOC_NRF52840 nrfx/mdk/system_nrf52840.c) + if(CONFIG_HAS_NRFX) zephyr_include_directories(nrfx) zephyr_include_directories(nrfx/drivers/include)