soc: arm: stm32l5: enable ICACHE

Enable Instruction Cache
Warning: no flash driver yet available for STM32l5
But cache coherency management (cache invalidate)
will be rerquired when implementing flash driver.
ICAHE must be disabled for any flash write opeartion.

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>

soc/arm/st_stm32/stm32l5/soc.c

@@ -15,7 +15,7 @@
 #include <stm32_ll_pwr.h>
 #include <arch/cpu.h>
 #include <arch/arm/aarch32/cortex_m/cmsis.h>
-
+#include <stm32l5xx_ll_icache.h>
 #include <logging/log.h>
 
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
@@ -35,6 +35,11 @@ static int stm32l5_init(const struct device *arg)
 
 	ARG_UNUSED(arg);
 
+	/* Enable ICACHE */
+	while (LL_ICACHE_IsActiveFlag_BUSY()) {
+	}
+	LL_ICACHE_Enable();
+
 	key = irq_lock();
 
 	/* Install default handler that simply resets the CPU